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Analysis and Design of a 15.2-to-18.2-GHz Inverse-Class-F VCO With a Balanced Dual-Core Topology Suppressing the Flicker Noise Upconversion Journal article
Meng, Xi, Li, Haoran, Chen, Peng, Yin, Jun, Mak, Pui In, Martins, Rui P.. Analysis and Design of a 15.2-to-18.2-GHz Inverse-Class-F VCO With a Balanced Dual-Core Topology Suppressing the Flicker Noise Upconversion[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2023, 70(12), 5110-5123.
Authors:  Meng, Xi;  Li, Haoran;  Chen, Peng;  Yin, Jun;  Mak, Pui In; et al.
Favorite | TC[WOS]:1 TC[Scopus]:2  IF:5.2/4.5 | Submit date：2024/02/22
Dual-core Coupled  Flicker Noise Upconversion  Inverse-class-f (Class-f-1)  Phase Noise (Pn)  Second Harmonic Resonance  Switched Capacitor  Voltage-controlled Oscillator (Vco)  
Power-Efficient RF and mm-Wave VCOs/PLL Book chapter
出自: Analog Circuits and Signal Processing, Switzerland:Springer, 2023, 页码:51-89
Authors:  Hao Guo;  Zunsong Yang;  Chee Cheow Lim;  Harikrishnan Ramiah;  Yatao Peng; et al.
Favorite | TC[Scopus]:0 | Submit date：2023/08/03
Harmonic Tuning  Inverse Class-f  Jitter  Millimeter Wave (mm-Wave)  Mode-switching  Phase Noise  Phase-locked Loop (Pll)  Reference Spur  Subsampling  Voltage-controlled Oscillator (Vco)  
A 529-μW Fractional-N All-Digital PLL Using TDC Gain Auto-Calibration and an Inverse-Class-F DCO in 65-nm CMOS Journal article
Chen, Peng, Meng, Xi, Yin, Jun, Mak, Pui In, Martins, Rui P., Staszewski, Robert Bogdan. A 529-μW Fractional-N All-Digital PLL Using TDC Gain Auto-Calibration and an Inverse-Class-F DCO in 65-nm CMOS[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2022, 69(1), 51-63.
Authors:  Chen, Peng;  Meng, Xi;  Yin, Jun;  Mak, Pui In;  Martins, Rui P.; et al.
Favorite | TC[WOS]:16 TC[Scopus]:15  IF:5.2/4.5 | Submit date：2021/09/20
Adpll  Bluetooth Le (bLe)  Dco  Fractionaln Pll  Phase Noise (Pn)  Tdc  Dtc  Inverse-class-f  Low Power  The Iot  
An Inverse-Class-F CMOS Oscillator With Intrinsic-High-Q First Harmonic and Second Harmonic Resonances Journal article
Lim, Chee Cheow, Ramiah, Harikrishnan, Yin, Jun, Mak, Pui-In, Martins, Rui P.. An Inverse-Class-F CMOS Oscillator With Intrinsic-High-Q First Harmonic and Second Harmonic Resonances[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2018, 53(12), 3528-3539.
Authors:  Lim, Chee Cheow;  Ramiah, Harikrishnan;  Yin, Jun;  Mak, Pui-In;  Martins, Rui P.
Favorite | TC[WOS]:48 TC[Scopus]:55  IF:4.6/5.6 | Submit date：2019/01/17
Figure Of Merit (Fom)  Flicker Noise Upcon-version  Inverse-class-f (Class-f-1) Oscillator  Phase Noise (Pn)  Second Harmonic Resonance  Voltage-biased Oscillator  
An Inverse-Class-F CMOS Oscillator with Intrinsic-High-Q 1st-Harmonic and 2nd-Harmonic Resonances Journal article
Chee Cheow Lim, Harikrishnan Ramiah, Jun Yin, Pui-In Mak, Rui P. Martins. An Inverse-Class-F CMOS Oscillator with Intrinsic-High-Q 1st-Harmonic and 2nd-Harmonic Resonances[J]. IEEE Journal of Solid-State Circuits, 2018, 53(12), 3528 - 3539.
Authors:  Chee Cheow Lim;  Harikrishnan Ramiah;  Jun Yin;  Pui-In Mak;  Rui P. Martins
Favorite | TC[WOS]:48 TC[Scopus]:55  IF:4.6/5.6 | Submit date：2019/03/12
Figure Of Merit (Fom)  Flicker Noise Upconversion  Inverse-class-f (Class-f−1) Oscillator  Phase Noise (Pn)  Second Harmonic Resonance  Voltage-biased Oscillator  
529-μW Fractional-N All-Digital PLL Using TDC Gain Auto-Calibration and an Inverse-Class-F DCO in 65-nm CMOS Journal article
Chen, P., Meng, X., Yin, J., Mak, P. I., Martins, R. P., Staszewski, R. B.. 529-μW Fractional-N All-Digital PLL Using TDC Gain Auto-Calibration and an Inverse-Class-F DCO in 65-nm CMOS[J]. IEEE Transactions on Circuits and Systems I: Regular Papers.
Authors:  Chen, P.;  Meng, X.;  Yin, J.;  Mak, P. I.;  Martins, R. P.; et al.
Favorite |   IF:5.2/4.5 | Submit date：2022/01/25
ADPLL  Bluetooth LE (BLE)  DCO  fractionalN PLL  phase noise (PN)  TDC  DTC  inverse-class-F  low power  the IoT