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A 50Gb/s CMOS Optical Receiver With Si-Photonics PD for High-Speed Low-Latency Chiplet I/O Journal article
Chen, Sikai, You, Mingyang, Yang, Yunqi, Jin, Ye, Lin, Ziyi, Li, Yihong, Li, Leliang, Li, Guike, Xie, Yujun, Zhang, Zhao, Wang, Binhao, Tang, Ningfeng, Liu, Faju, Fang, Zheyu, Liu, Jian, Wu, Nanjian, Chen, Yong, Liu, Liyuan, Zhu, Ninghua, Li, Ming, Qi, Nan. A 50Gb/s CMOS Optical Receiver With Si-Photonics PD for High-Speed Low-Latency Chiplet I/O[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2023, 70(11), 4271-4282.
Authors:  Chen, Sikai;  You, Mingyang;  Yang, Yunqi;  Jin, Ye;  Lin, Ziyi; et al.
Favorite | TC[WOS]:3 TC[Scopus]:3  IF:5.2/4.5 | Submit date：2023/12/04
Baud-rate  Cdr  Chiplet  Cmos  Multi-chip Module (Mcm)  Optical I/o  Optical Receiver  Silicon Photonics  Tia  
O Verbo Português“Pensar”e os Seus Correspondentes Verbais em Chinês“Renwei”e“Yiwei” Book chapter
出自: Linguística Contrastiva: Estudos Português-Chinês, Macau:University of Macau, 2022, 页码:93-109
Authors:  Zhang, Jing;  Grosso, Maria José
Favorite |  | Submit date：2022/08/08
Verbo De Opinião  Pensar  Rènwé  Yǐwéi  
A Slew Rate Variation Compensated 2 x VDD I/O Buffer Using Deterministic P/N-PVT Variation Detection Method Journal article
Lee, Tzung-Je, Tsai, Tsung-Yi, Lin, Wei, Chio, U-Fat, Wang, Chua-Chin. A Slew Rate Variation Compensated 2 x VDD I/O Buffer Using Deterministic P/N-PVT Variation Detection Method[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2019, 66(1), 116-120.
Authors:  Lee, Tzung-Je;  Tsai, Tsung-Yi;  Lin, Wei;  Chio, U-Fat;  Wang, Chua-Chin
Favorite | TC[WOS]:13 TC[Scopus]:14  IF:4.0/3.7 | Submit date：2019/01/17
I/o Buffer  Mixed-voltage Tolerant  Pvt Variation  Leakage  Slew Rate Compensation  
A Migratory HeterogeneityAware Data Layout Scheme for Parallel File Systems Conference paper
He, S., Sun, X., Wang, Y., Xu, C.Z.. A Migratory HeterogeneityAware Data Layout Scheme for Parallel File Systems[C], 2018.
Authors:  He, S.;  Sun, X.;  Wang, Y.;  Xu, C.Z.
Favorite |  | Submit date：2022/01/26
Parallel I/O System  Parallel File System  Solid State Drive  Data Layout  
A Dynamic Leakage and Slew Rate Compensation Circuit for 40-nm CMOS Mixed-Voltage Output Buffer Journal article
Lee, Tzung-Je, Tsai, Tsung-Yi, Lin, Wei, Chio, U-Fat, Wang, Chua-Chin. A Dynamic Leakage and Slew Rate Compensation Circuit for 40-nm CMOS Mixed-Voltage Output Buffer[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017, 25(11), 3166-3174.
Authors:  Lee, Tzung-Je;  Tsai, Tsung-Yi;  Lin, Wei;  Chio, U-Fat;  Wang, Chua-Chin
Favorite | TC[WOS]:7 TC[Scopus]:8  IF:2.8/2.8 | Submit date：2018/10/30
Dynamic Leakage Reduction  I/o Buffer  Mixed-voltage Tolerant  Process-voltage-temperature (Pvt) Variation  Slew Rate Compensation  
O Herói colectivo de Levantado do Chão na construção de Abril Journal article
ANA SALDANHA. O Herói colectivo de Levantado do Chão na construção de Abril[J]. VÉRTICE, 2011(158), 35-52.
Authors:  ANA SALDANHA
Favorite |  | Submit date：2023/04/10
Literatura Portuguesa  José Saramago  Herói Colectivo  Reforma Agrária  Revolução Portuguesa  
Optimizing data loading and memory allocation for out-of-core simplification Journal article
Wang H., Cai K., Wang W., Wu E.. Optimizing data loading and memory allocation for out-of-core simplification[J]. Jisuanji Fuzhu Sheji Yu Tuxingxue Xuebao/Journal of Computer-Aided Design and Computer Graphics, 2005, 17(8), 1736-1743.
Authors:  Wang H.;  Cai K.;  Wang W.;  Wu E.
Favorite |  | Submit date：2019/02/13
Dynamic optimization  I/O  Memory allocation  Out-of-core simplification