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A 13-Bit ENOB Third-Order Noise-Shaping SAR ADC Employing Hybrid Error Control Structure and LMS-Based Foreground Digital Calibration Journal article
Zhang, Qihui, Ning, Ning, Zhang, Zhong, Li, Jing, Wu, Kejun, Chen, Yong, Yu, Qi. A 13-Bit ENOB Third-Order Noise-Shaping SAR ADC Employing Hybrid Error Control Structure and LMS-Based Foreground Digital Calibration[J]. IEEE Journal of Solid-State Circuits, 2022, 57(7), 2181-2195.
Authors:  Zhang, Qihui;  Ning, Ning;  Zhang, Zhong;  Li, Jing;  Wu, Kejun; et al.
Favorite | TC[WOS]:22 TC[Scopus]:24  IF:4.6/5.6 | Submit date：2022/05/17
Analog-to-digital Converter (Adc)  Calibration  Capacitors  Delays  Dither-based Digital Calibration  Finite Impulse Response Filters  Hybrid Error Control Structure  Noise Shaping  Noise Shaping (Ns)  Quantization (Signal)  Successive Approximation Register (Sar).  Topology  
A Robust Hybrid CT/DT 0-2 MASH DSM with Passive Noise-Shaping SAR ADC Conference paper
Li, Ke, Sin, Sai Weng, Qi, Liang, Zhao, Weibing, Wang, Guoxing, Martins, R. P.. A Robust Hybrid CT/DT 0-2 MASH DSM with Passive Noise-Shaping SAR ADC[C], 2022, 551-555.
Authors:  Li, Ke;  Sin, Sai Weng;  Qi, Liang;  Zhao, Weibing;  Wang, Guoxing; et al.
Favorite | TC[WOS]:3 TC[Scopus]:3 | Submit date：2023/01/30
Delta-sigma Modulator (Dsm)  Hybrid Adc  Multi-stage Noise-shaping (Mash)  Noise-shaping Successive Approximation Register (Ns-sar)  
Recent Advances in High-Resolution Hybrid Discrete-Time Noise-Shaping ADCs Journal article
Jiang, D., Sin, S. W., Qi, L., Wang, G., Martins, R. P.. Recent Advances in High-Resolution Hybrid Discrete-Time Noise-Shaping ADCs[J]. IEEE Open Journal of the Solid-State Circuits Society, 2021, 129-139.
Authors:  Jiang, D.;  Sin, S. W.;  Qi, L.;  Wang, G.;  Martins, R. P.
Favorite |  | Submit date：2022/01/25
ADC  analog-to-digital converter  DAC  digital-to-analog-converter  hybrid ADC  incremental ADC (I-ADC)  delta-sigma modulator  time-Interleaving  extrapolating  noise shaping  successive approximation register  SAR.  
A 2.56mW 40MHz-Bandwidth 75dB-SNDR Partial- Interleaving SAR-Assisted NS Pipeline ADC With Background Inter-Stage Offset Calibration Conference paper
Song, Y., Zhu, Y., Chan, C. H., Martins, R. P.. A 2.56mW 40MHz-Bandwidth 75dB-SNDR Partial- Interleaving SAR-Assisted NS Pipeline ADC With Background Inter-Stage Offset Calibration[C], 2020.
Authors:  Song, Y.;  Zhu, Y.;  Chan, C. H.;  Martins, R. P.
Favorite |  | Submit date：2022/01/25
analogue-digital conversion  calibration  CMOS digital integrated circuits  digital-analogue conversion  low-power electronics  preamplifiers  background inter-stage offset calibration  noise-shaping SAR hybrid architecture  NS-SAR  SNDR  power-hungry preamplifiers  low-noise targets  Schreier FoM  0-1 MASH SDM  pipeline-SAR structure  single-channel ADC  power-hungry residue amplifier  ADC power  area-hungry bit weight calibration  dynamic amplifier  pipeline operation  power efficiency  partial interleaving structu  
Tutorials in Circuits and Systems: Selected Topics in Power, RF, and Mixed-Signal ICs Book
Yan Lu, Chi-Seng Lam. Tutorials in Circuits and Systems: Selected Topics in Power, RF, and Mixed-Signal ICs[M]. River Publishers:River Publishers, 2017.
Authors:  Yan Lu;  Chi-Seng Lam
Favorite |  | Submit date：2022/08/12
Dc-dc Switching Converters  Analog And Digital Regulators  Analog And Digital Frequency Synthesizers  Hybrid Adc Architecture  Cmos Image Sensors  Cmos Temperature Sensors  Cmos Millimeter-wave Power Amplifiers  Zigbee  Ble Transmitter  Iot Applications  
Selected Topics in Power, RF, and Mixed-Signal ICs Book
Yan Lu, Chi-Seng Lam. Selected Topics in Power, RF, and Mixed-Signal ICs[M]. Gistrup, Denmark:River Publishers, 2017.
Authors:  Yan Lu;  Chi-Seng Lam
Favorite |  | Submit date：2019/04/03
Dc-dc Switching Converters  Iot Applications  Analog And Digital Regulators  Analog And Digital Frequency Synthesizers  Hybrid Adc Architecture  Cmos Image Sensors  Cmos Temperature Sensors  Cmos Millimeter-wave Power Amplifiers  Zigbee  Ble Transmitter