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An Inherent Gain Error Tolerance Noise-Shaping SAR-Assisted Pipeline ADC with Code-Counter-Based Offset Calibration Journal article
Zhang, Hongshuai, Zhu, Yan, Chan, Chi Hang, Martins, Rui P.. An Inherent Gain Error Tolerance Noise-Shaping SAR-Assisted Pipeline ADC with Code-Counter-Based Offset Calibration[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2022, 57(5), 1480-1491.
Authors:  Zhang, Hongshuai;  Zhu, Yan;  Chan, Chi Hang;  Martins, Rui P.
Favorite | TC[WOS]:8 TC[Scopus]:10  IF:4.6/5.6 | Submit date：2022/05/13
Amplifier Linearity Enhancement  Analog-to-digital Converter (Adc)  Background Offset Calibration  Digital Reconstruction Filter  Dwa  Energy And Area Efficient  Inherent Gain Error Tolerant  Inter-stage Gain Error  Noise Shaping (Ns)  Oversampling  Partial Interleaving  Pipelined Successive Approximation (Sar)  Quantization Leakage Error  
A Calibration-Free Ring-Oscillator PLL with Gain Tracking Achieving 9% Jitter Variation over PVT Journal article
Xiaofeng Yang, Chi-Hang Chan, Yan Zhu, Rui Paulo Martins. A Calibration-Free Ring-Oscillator PLL with Gain Tracking Achieving 9% Jitter Variation over PVT[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2020, 67(11), 3753-3763.
Authors:  Xiaofeng Yang;  Chi-Hang Chan;  Yan Zhu;  Rui Paulo Martins
Favorite | TC[WOS]:8 TC[Scopus]:8  IF:5.2/4.5 | Submit date：2021/03/04
Calibration-free  Discrete-time  Gain Tracking  Jitter  Open-loop  Phase Noise Cancellation (Pnc)  Phase-locked Loop (Pll)  Pvt  Reference Spur  Ring Voltage-controlled Oscillator (Rvco)  
A 0.12-mm2 1.2-to-2.4 mW 1.3-to-2.65 GHz Fractional-N Bang-Bang Digital PLL with 8-μs Settling Time for Multi-ISM-Band ULP Radios Journal article
Un, K. F., Qi, G., Yin, J., Yang, S., Yu, S., Ieong, C. -I., Mak, P. I., Martins, R. P.. A 0.12-mm2 1.2-to-2.4 mW 1.3-to-2.65 GHz Fractional-N Bang-Bang Digital PLL with 8-μs Settling Time for Multi-ISM-Band ULP Radios[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2019, 3307-3316.
Authors:  Un, K. F.;  Qi, G.;  Yin, J.;  Yang, S.;  Yu, S.; et al.
Favorite |   IF:5.2/4.5 | Submit date：2022/01/25
digital phase-locked loop (DPLL)  bang-bang  digital-to-time converter (DTC)  gain calibration  voltage-controlled oscillator (VCO)  ring VCO  ultra-low-power (ULP)  ultra-fast settling  
A 0.12-mm2 1.2-to-2.4-mW 1.3-to-2.65-GHz Fractional-N bang-bang digital PLL with 8-μs settling time for multi-ISM-Band ULP radios Journal article
Un,Ka Fai, Qi,Gengzhen, Yin,Jun, Yang,Shiheng, Yu,Shupeng, Ieong,Chio In, Mak,Pui In, Martins,Rui P.. A 0.12-mm2 1.2-to-2.4-mW 1.3-to-2.65-GHz Fractional-N bang-bang digital PLL with 8-μs settling time for multi-ISM-Band ULP radios[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2019, 66(9), 3307-3316.
Authors:  Un,Ka Fai;  Qi,Gengzhen;  Yin,Jun;  Yang,Shiheng;  Yu,Shupeng; et al.
Favorite | TC[WOS]:11 TC[Scopus]:12  IF:5.2/4.5 | Submit date：2021/03/09
Bang-bang  Digital Phase-locked Loop (Dpll)  Digital-to-time Converter (Dtc)  Gain Calibration  Ring Vco  Ultra-fast Settling  Ultra-low-power (Ulp)  Voltage-controlled Oscillator (Vco)  
Missing-Code-Occurrence Probability Calibration Technique for DAC Nonlinearity With Supply and Reference Circuit Analysis in a SAR ADC Conference paper
Wang, Guancheng, Li, Cheng, Zhu, Yan, Zhong, Jianyu, Lu, Yan, Chan, Chi-Hang, Martins, Rui P.. Missing-Code-Occurrence Probability Calibration Technique for DAC Nonlinearity With Supply and Reference Circuit Analysis in a SAR ADC[C], 445 HOES LANE, PISCATAWAY, NJ 08855-4141 USA:IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2018, 3707-3719.
Authors:  Wang, Guancheng;  Li, Cheng;  Zhu, Yan;  Zhong, Jianyu;  Lu, Yan; et al.
Favorite | TC[WOS]:5 TC[Scopus]:5 | Submit date：2018/10/30
Gain Error Calibration  Testing Signal Generation  Sar Adc  Bridge Dac  Low-dropout (Ldo) Regulator  
Gain Error Calibrations for Two-Step ADCs: Optimizations Either in Accuracy or Chip Area Journal article
Wang, Guan Cheng, Zhu, Yan, Chan, Chi-Hang, Seng-Pan, U., Martins, Rui P.. Gain Error Calibrations for Two-Step ADCs: Optimizations Either in Accuracy or Chip Area[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2018, 26(11), 2279-2289.
Authors:  Wang, Guan Cheng;  Zhu, Yan;  Chan, Chi-Hang;  Seng-Pan, U.;  Martins, Rui P.
Favorite | TC[WOS]:2 TC[Scopus]:2  IF:2.8/2.8 | Submit date：2019/01/17
Bridge Digital-to-analog Converter (Dac)  Gain Error Calibration  Successive Approximation Register (Sar)  Analog-to-digital Converters (Adcs)  Testing Signal Generation (Tsg)  
Missing-Code-occurrence probability calibration technique for DAC nonlinearity with supply and reference circuit analysis in a SAR ADC Journal article
Wang G., Li C., Zhu Y., Zhong J., Lu Y., Chan C.-H., Martins R.P.. Missing-Code-occurrence probability calibration technique for DAC nonlinearity with supply and reference circuit analysis in a SAR ADC[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2018, 65(11), 3707-3719.
Authors:  Wang G.;  Li C.;  Zhu Y.;  Zhong J.;  Lu Y.; et al.
Favorite | TC[WOS]:5 TC[Scopus]:5 | Submit date：2019/02/11
Bridge Dac  Gain Error Calibration  Low-dropout (Ldo) Regulator  Sar Adc  Testing Signal Generation  
Gain-Error-Calibrations for Two-step ADCs: Optimizations either in Accuracy or Chip Area Journal article
Wang, G. C., Zhu, Y., Chan, C. H., Martins, R. P.. Gain-Error-Calibrations for Two-step ADCs: Optimizations either in Accuracy or Chip Area[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2018, 2279-2289.
Authors:  Wang, G. C.;  Zhu, Y.;  Chan, C. H.;  Martins, R. P.
Favorite |   IF:2.8/2.8 | Submit date：2022/01/25
Gain error calibration  testing signal generation  SAR ADC  bridge-DAC  
A four-band TD-LTE Transmitter with wide dynamic range and LPF bandwidth calibration Conference paper
Liang, Zhen, Li, Bin, Huang, Mo, Ye, Hui, Xu, Ken, Liu, Yutao, Lu, Yan. A four-band TD-LTE Transmitter with wide dynamic range and LPF bandwidth calibration[C], 345 E 47TH ST, NEW YORK, NY 10017 USA:IEEE, 2017.
Authors:  Liang, Zhen;  Li, Bin;  Huang, Mo;  Ye, Hui;  Xu, Ken; et al.
Favorite | TC[WOS]:0 TC[Scopus]:2 | Submit date：2018/10/30
Td-lte  Transmitter  Wide Dynamic Gain Range  Bandwidth Calibration  
A 10-bit 500-MS/s Partial-Interleaving Pipelined SAR ADC With Offset and Reference Mismatch Calibrations Journal article
Zhu, Yan, Chan, Chi-Hang, Pan, Seng U., Martins, Rui Paulo. A 10-bit 500-MS/s Partial-Interleaving Pipelined SAR ADC With Offset and Reference Mismatch Calibrations[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017, 25(1), 354-363.
Authors:  Zhu, Yan;  Chan, Chi-Hang;  Pan, Seng U.;  Martins, Rui Paulo
Favorite | TC[WOS]:11 TC[Scopus]:14  IF:2.8/2.8 | Submit date：2018/10/30
Offset Calibration  Partial Interleaving (Pi)  Pipelined-sar  Stage-gain Error Calibration