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面向云服务的性能与隔离性定制化硬件资源抽象方法 Patent
专利类型: 发明专利Invention,
Authors:  YE KEJIANG;  SU LINYU;  LIN YANYING;  XU CHENGZHONG
Favorite |  | Submit date：2022/08/29
Cloud Services  Hardware Resource Abstraction  Fpga  
An FPGA-Based Transformer Accelerator With Parallel Unstructured Sparsity Handling for Question-Answering Applications Journal article
Cao, Rujian, Zhao, Zhongyu, Un, Ka Fai, Yu, Wei Han, Martins, Rui P., Mak, Pui In. An FPGA-Based Transformer Accelerator With Parallel Unstructured Sparsity Handling for Question-Answering Applications[J]. IEEE Transactions on Circuits and Systems II-Express Briefs, 2024, 71(11), 4688-4692.
Authors:  Cao, Rujian;  Zhao, Zhongyu;  Un, Ka Fai;  Yu, Wei Han;  Martins, Rui P.; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:4.0/3.7 | Submit date：2024/10/10
Sparse Matrices  Computational Modeling  Transformers  Hardware  Energy Efficiency  Circuits  Throughput  Dataflow  Digital Accelerator  Energy-efficient  Field-programmable Gate Array (Fpga)  Sparsity  Transformer  
Modeling Attack Resistant Strong PUF Exploiting Stagewise Obfuscated Interconnections With Improved Reliability Journal article
Xu, Chongyao, Zhang, Litao, Law, Man Kay, Zhao, Xiaojin, Mak, Pui In, Martins, Rui P.. Modeling Attack Resistant Strong PUF Exploiting Stagewise Obfuscated Interconnections With Improved Reliability[J]. IEEE Internet of Things Journal, 2023, 10(18), 16300 - 16315.
Authors:  Xu, Chongyao;  Zhang, Litao;  Law, Man Kay;  Zhao, Xiaojin;  Mak, Pui In; et al.
Favorite | TC[WOS]:10 TC[Scopus]:15  IF:8.2/9.0 | Submit date：2023/08/03
Field-programmable Gate Array (Fpga)  Machine Learning (Ml) Modeling Attack  Obfuscated Interconnection (Oi)  Physical Unclonable Function (Puf)  
TAPU: A Transmission-Analytics Processing Unit for Accelerating Multi-functions in IoT Gateways Journal article
Liang,Huanghuang, Sang,Qianlong, Hu,Chuang, Gong,Yili, Cheng,Dazhao, Zhou,Xiaobo, Wang,Yu. TAPU: A Transmission-Analytics Processing Unit for Accelerating Multi-functions in IoT Gateways[J]. IEEE Internet of Things Journal, 2023, 10(20), 18181 - 18197.
Authors:  Liang,Huanghuang;  Sang,Qianlong;  Hu,Chuang;  Gong,Yili;  Cheng,Dazhao; et al.
Favorite | TC[WOS]:1 TC[Scopus]:1  IF:8.2/9.0 | Submit date：2023/08/03
Fpga Offloading  Hardware Acceleration  Internet Of Things (Iot) Gateways  Network Functions (Nfs)  Video Analytics (Vas)  
Transfer-Path-Based Hardware-Reuse Strong PUF Achieving Modeling Attack Resilience With >200 Million Training CRPs Journal article
Xu, Chongyao, Zhang, Jieyun, Law, Man-Kay, Zhao, Xiaojin, Mak, Pui-In, Martins, Rui P.. Transfer-Path-Based Hardware-Reuse Strong PUF Achieving Modeling Attack Resilience With >200 Million Training CRPs[J]. IEEE Transactions on Information Forensics and Security, 2023, 18, 2188 - 2203.
Authors:  Xu, Chongyao;  Zhang, Jieyun;  Law, Man-Kay;  Zhao, Xiaojin;  Mak, Pui-In; et al.
Favorite | TC[WOS]:4 TC[Scopus]:6  IF:6.3/7.3 | Submit date：2023/03/29
Field-programmable Gate Array (Fpga)  Hardware Reuse  Machine Learning (Ml) Attack  Multiplier  Physical Unclonable Function (Puf)  Response Stream (Rs)  Transfer Path (Tp)  
An FPGA-Based Transformer Accelerator Using Output Block Stationary Dataflow for Object Recognition Applications Journal article
Zhao, Zhongyu, Cao, Rujian, Un, Ka Fai, Yu, Wei Han, Mak, Pui In, Martins, Rui P.. An FPGA-Based Transformer Accelerator Using Output Block Stationary Dataflow for Object Recognition Applications[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2023, 70(1), 281-285.
Authors:  Zhao, Zhongyu;  Cao, Rujian;  Un, Ka Fai;  Yu, Wei Han;  Mak, Pui In; et al.
Favorite | TC[WOS]:8 TC[Scopus]:12  IF:4.0/3.7 | Submit date：2022/08/08
Transformers  Energy Efficiency  Broadcasting  Convolutional Neural Networks  Integrated Circuit Modeling  Field Programmable Gate Arrays  Random Access Memory  Dataflow  Digital Accelerator  Energy-efficient  Field-programmable Gate Array (Fpga)  Energy Efficiency  Image Recognition  Transformer  
Caching Hybrid Rotation: A Memory Access Optimization Method for CNN on FPGA Journal article
Dong,Dong, Jiang,Hongxu, Wei,Xuekai. Caching Hybrid Rotation: A Memory Access Optimization Method for CNN on FPGA[J]. Journal of Circuits, Systems and Computers, 2023, 32(13).
Authors:  Dong,Dong;  Jiang,Hongxu;  Wei,Xuekai
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:0.9/0.9 | Submit date：2023/08/03
Caching Hybrid Rotation  Cnn  Feature Map Partition  Fpga  Memory Access  
An FPGA-Based Energy-Efficient Reconfigurable Depthwise Separable Convolution Accelerator for Image Recognition Journal article
Lei Xuan, Ka-Fai Un, Chi-Seng Lam, Rui P. Martins. An FPGA-Based Energy-Efficient Reconfigurable Depthwise Separable Convolution Accelerator for Image Recognition[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2022, 69(10), 4003-4007.
Authors:  Lei Xuan;  Ka-Fai Un;  Chi-Seng Lam;  Rui P. Martins
Favorite | TC[WOS]:26 TC[Scopus]:26  IF:4.0/3.7 | Submit date：2022/06/14
Frequency Modulation  Field Programmable Gate Arrays  Energy Efficiency  Memory Management  Random Access Memory  Arrays  Computational Cost  Convolutional Neural Network (Cnn)  Field-programmable Gate Array (Fpga)  Mobilenetv2  Neural Network  Quantization  
Differences in MBUs induced by high-energy and medium-energy heavy ions in 28 nm FPGAs Journal article
Shuai Gao, Jin-Hu Yang, Bing Ye, Chang Cai, Ze He, Jie Liu, Tian-Qi Liu, Xiao-Yu Yan, You-Mei Sun, Guo-Qing Xiao. Differences in MBUs induced by high-energy and medium-energy heavy ions in 28 nm FPGAs[J]. Nuclear Science and Techniques, 2022, 33(9), 112.
Authors:  Shuai Gao;  Jin-Hu Yang;  Bing Ye;  Chang Cai;  Ze He; et al.
Favorite | TC[WOS]:1 TC[Scopus]:1  IF:3.6/2.4 | Submit date：2022/10/06
Fpga  High-energy Heavy-ion Radiation  Mbu  Ionization Track  
A 7.4-Bit ENOB 600 MS/s FPGA-Based Online Calibrated Slope ADC without External Components Journal article
Zhang, Mengdi, Zhao, Ye, Chen, Yong, Crovetti, Paolo, Wang, Yanji, Ning, Xinshun, Qiao, Shushan. A 7.4-Bit ENOB 600 MS/s FPGA-Based Online Calibrated Slope ADC without External Components[J]. Sensors (Basel, Switzerland), 2022, 22(22), 8936.
Authors:  Zhang, Mengdi;  Zhao, Ye;  Chen, Yong;  Crovetti, Paolo;  Wang, Yanji; et al.
Favorite | TC[WOS]:1 TC[Scopus]:1  IF:3.4/3.7 | Submit date：2022/09/07
Analog-to-digital Converter (Adc)  Differential Nonlinearity (Dnl)  Effective Number Of Bits (Enob)  Fpga  Integral Nonlinearity (Inl)  Time-to-digital Converter (Tdc)