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A 12-bit 1GS/s ADC With Background Distortion and Split-ADC-Like Gain Calibration Journal article
Wei, Lai, Zheng, Zihao, Markulic, Nereo, Lagos, Jorge, Martens, Ewout, Martins, Rui Paulo, Zhu, Yan, Craninckx, Jan, Chan, Chi Hang. A 12-bit 1GS/s ADC With Background Distortion and Split-ADC-Like Gain Calibration[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2023, 70(12), 4679-4691.
Authors:  Wei, Lai;  Zheng, Zihao;  Markulic, Nereo;  Lagos, Jorge;  Martens, Ewout; et al.
Favorite | TC[WOS]:3 TC[Scopus]:2  IF:5.2/4.5 | Submit date：2024/02/23
Analog-to-digital Converter  Cmos Analog Integrated Circuits  Distortion  Input Buffer  Split-adc-like Calibration  
A 0.004-mm2 3.65-mW 7-Bit 2-GS/s Single-Channel GRO-Based Time-Domain ADC Incorporating Dead-Zone Elimination and On-Chip Folding-Offset Calibration in 28-nm CMOS Journal article
Zhang,Chenghao, Wei,Jiangbo, Chen,Yong, Liu,Maliang, Yang,Yintang. A 0.004-mm2 3.65-mW 7-Bit 2-GS/s Single-Channel GRO-Based Time-Domain ADC Incorporating Dead-Zone Elimination and On-Chip Folding-Offset Calibration in 28-nm CMOS[J]. IEEE Journal of Solid-State Circuits, 2023, 58(11), 3179-3193.
Authors:  Zhang,Chenghao;  Wei,Jiangbo;  Chen,Yong;  Liu,Maliang;  Yang,Yintang
Favorite | TC[WOS]:2 TC[Scopus]:2  IF:4.6/5.6 | Submit date：2023/08/03
Analog-to-digital Converter (Adc)  Calibration  Cmos  Folding  Gated Ring Oscillator (Gro)  Interpolation  Pulse Generator (Pg)  Time Domain (Td)  Voltage Domain (Vd)  
Low-Power Nyquist ADCs Book chapter
出自: Analog Circuits and Signal Processing, Switzerland:Springer, 2023, 页码:131-180
Authors:  Minglei Zhang;  Chi-Hang Chan;  Yan Zhu;  Rui P. Martins
Favorite | TC[Scopus]:1 | Submit date：2023/08/03
Analog-to-digital Converter (Adc)  Calibration  Low Supply Voltage  Pipeline  Successive Approximation Register (Sar)  Time-domain Converter (Tdc)  
High-Speed and Time-Interleaved ADCs Using Additive-Neural-Network-Based Calibration for Nonlinear Amplitude and Phase Distortion Journal article
Zhai, Danfeng, Jiang, Wenning, Jia, Xinru, Lan, Jingchao, Guo, Mingqiang, Sin, Sai Weng, Ye, Fan, Liu, Qi, Ren, Junyan, Chen, Chixiao. High-Speed and Time-Interleaved ADCs Using Additive-Neural-Network-Based Calibration for Nonlinear Amplitude and Phase Distortion[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2022, 69(12), 4944-4957.
Authors:  Zhai, Danfeng;  Jiang, Wenning;  Jia, Xinru;  Lan, Jingchao;  Guo, Mingqiang; et al.
Adobe PDF | Favorite | TC[WOS]:12 TC[Scopus]:15  IF:5.2/4.5 | Submit date：2023/01/30
Analog-to-digital Converter (Adc)  Nonlinear Digital Calibration  Neural Network  Static And Dynamic Calibrations  Compute-in-memory  
A 1.2-A Calibration-Free Hybrid LDO With In-Loop Quantization and Auxiliary Constant Current Control Achieving High Accuracy and Fast DVS Journal article
Xiangyu Mao, Yan Lu, Rui P. Martins. A 1.2-A Calibration-Free Hybrid LDO With In-Loop Quantization and Auxiliary Constant Current Control Achieving High Accuracy and Fast DVS[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2022, 69(11), 4443-4452.
Authors:  Xiangyu Mao;  Yan Lu;  Rui P. Martins
Favorite | TC[WOS]:6 TC[Scopus]:7  IF:5.2/4.5 | Submit date：2022/09/09
Calibration  Codes  Digital  Distributed Power Delivery  Dynamic Voltage And Frequency Scaling (Dvfs)  Fully-integrated Voltage Regulator (Fivr)  Hybrid Control  Hybrid Power Systems  Low-dropout Regulator (Ldo)  Power Transistors  Quantization (Signal)  Thermometers  Voltage Control  
An Inherent Gain Error Tolerance Noise-Shaping SAR-Assisted Pipeline ADC with Code-Counter-Based Offset Calibration Journal article
Zhang, Hongshuai, Zhu, Yan, Chan, Chi Hang, Martins, Rui P.. An Inherent Gain Error Tolerance Noise-Shaping SAR-Assisted Pipeline ADC with Code-Counter-Based Offset Calibration[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2022, 57(5), 1480-1491.
Authors:  Zhang, Hongshuai;  Zhu, Yan;  Chan, Chi Hang;  Martins, Rui P.
Favorite | TC[WOS]:8 TC[Scopus]:10  IF:4.6/5.6 | Submit date：2022/05/13
Amplifier Linearity Enhancement  Analog-to-digital Converter (Adc)  Background Offset Calibration  Digital Reconstruction Filter  Dwa  Energy And Area Efficient  Inherent Gain Error Tolerant  Inter-stage Gain Error  Noise Shaping (Ns)  Oversampling  Partial Interleaving  Pipelined Successive Approximation (Sar)  Quantization Leakage Error  
A 13-Bit ENOB Third-Order Noise-Shaping SAR ADC Employing Hybrid Error Control Structure and LMS-Based Foreground Digital Calibration Journal article
Zhang, Qihui, Ning, Ning, Zhang, Zhong, Li, Jing, Wu, Kejun, Chen, Yong, Yu, Qi. A 13-Bit ENOB Third-Order Noise-Shaping SAR ADC Employing Hybrid Error Control Structure and LMS-Based Foreground Digital Calibration[J]. IEEE Journal of Solid-State Circuits, 2022, 57(7), 2181-2195.
Authors:  Zhang, Qihui;  Ning, Ning;  Zhang, Zhong;  Li, Jing;  Wu, Kejun; et al.
Favorite | TC[WOS]:22 TC[Scopus]:24  IF:4.6/5.6 | Submit date：2022/05/17
Analog-to-digital Converter (Adc)  Calibration  Capacitors  Delays  Dither-based Digital Calibration  Finite Impulse Response Filters  Hybrid Error Control Structure  Noise Shaping  Noise Shaping (Ns)  Quantization (Signal)  Successive Approximation Register (Sar).  Topology  
Mismatch Analysis of DTCs With an Improved BIST-TDC in 28-nm CMOS Journal article
Chen, Peng, Yin, Jun, Zhang, Feifei, Mak, Pui In, Martins, Rui P., Staszewski, Robert Bogdan. Mismatch Analysis of DTCs With an Improved BIST-TDC in 28-nm CMOS[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2022, 69(1), 196-206.
Authors:  Chen, Peng;  Yin, Jun;  Zhang, Feifei;  Mak, Pui In;  Martins, Rui P.; et al.
Favorite | TC[WOS]:5 TC[Scopus]:7  IF:5.2/4.5 | Submit date：2021/09/20
All-digital Pll (adPll)  Build-in Self-test (Bist)  Digital-to-time Converter (Dtc)  Fractional Spur  Jitter  Mismatch  Noise Shaping  Phase/frequency Detector (Pfd)  Phase Frequency Detectors  Self Calibration  Time-to-digital Converter (Tdc).  
A 40-MHz Bandwidth 75-dB SNDR Partial-Interleaving SAR-Assisted Noise-Shaping Pipeline ADC Journal article
Song,Yan, Zhu,Yan, Chan,Chi Hang, Martins,Rui P.. A 40-MHz Bandwidth 75-dB SNDR Partial-Interleaving SAR-Assisted Noise-Shaping Pipeline ADC[J]. IEEE Journal of Solid-State Circuits, 2021, 56(6), 1772-1783.
Authors:  Song,Yan;  Zhu,Yan;  Chan,Chi Hang;  Martins,Rui P.
Favorite | TC[WOS]:14 TC[Scopus]:17  IF:4.6/5.6 | Submit date：2021/03/09
Analog-to-digital Converter (Adc)  Noise-shaping (Ns)  Offset Calibration  Successive Approximation Register (Sar)-assisted Pipeline  Time Interleaving  
A 3.3-GS/s 6-b Fully Dynamic Pipelined ADC With Linearized Dynamic Amplifier Journal article
Zihao Zheng, Lai Wei, Jorge Lagos, Ewout Martens, Yan Zhu, Chi Hang Chan, Jan Craninckx, Rui P. Martins. A 3.3-GS/s 6-b Fully Dynamic Pipelined ADC With Linearized Dynamic Amplifier[J]. IEEE Journal of Solid-State Circuits, 2021.
Authors:  Zihao Zheng;  Lai Wei;  Jorge Lagos;  Ewout Martens;  Yan Zhu; et al.
Favorite | TC[WOS]:8 TC[Scopus]:9  IF:4.6/5.6 | Submit date：2021/09/20
Analog-to-digital Conversion  Calibration  Calibration  Dynamic Amplifier (Da)  Hardware  Linearity  Linearization Technique  Pipeline Processing  Pipelined Analog-to-digital Converter (Adc).  Quantization (Signal)  Signal Resolution  System-on-chip