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Efficient Federated Learning With Quality-Aware Generated Models: An Incentive Mechanism Journal article
Zhang, Hanwen, Li, Peichun, Dai, Minghui, Wu, Yuan, Qian, Liping. Efficient Federated Learning With Quality-Aware Generated Models: An Incentive Mechanism[J]. IEEE Internet of Things Journal, 2024.
Authors:  Zhang, Hanwen;  Li, Peichun;  Dai, Minghui;  Wu, Yuan;  Qian, Liping
Favorite | TC[Scopus]:0  IF:8.2/9.0 | Submit date：2024/10/10
Federated Learning  Incentive Mechanism  Generative Ai  Data Compensation  
Filling the Missing: Exploring Generative AI for Enhanced Federated Learning over Heterogeneous Mobile Edge Devices Journal article
Li Peichun, Zhang Hanwen, Wu Yuan, Qian Liping, Yu Rong, Niyato Dusit, Shen Xuemin. Filling the Missing: Exploring Generative AI for Enhanced Federated Learning over Heterogeneous Mobile Edge Devices[J]. IEEE Transactions on Mobile Computing, 2024, 23(10), 10001 - 10015.
Authors:  Li Peichun;  Zhang Hanwen;  Wu Yuan;  Qian Liping;  Yu Rong; et al.
Favorite | TC[WOS]:3 TC[Scopus]:9  IF:7.7/6.5 | Submit date：2024/05/16
Convergence  Data Compensation  Data Models  Energy Consumption  Federated Learning  Generative Ai  Generative Ai  Optimization  Performance Evaluation  Resource Management  Training  
0.058 mm(2) 13 Gbit/s inductorless analogue equaliser with low-frequency equalisation compensating 15 dB channel loss Journal article
Balachandran, Arya, Chen, Yong, Choi, Pilsoon, Boon, Chirn Chye. 0.058 mm(2) 13 Gbit/s inductorless analogue equaliser with low-frequency equalisation compensating 15 dB channel loss[J]. ELECTRONICS LETTERS, 2018, 54(2).
Authors:  Balachandran, Arya;  Chen, Yong;  Choi, Pilsoon;  Boon, Chirn Chye
Favorite | TC[WOS]:6 TC[Scopus]:9  IF:0.7/0.9 | Submit date：2018/10/30
Equalisers  Circuit Feedback  Analogue Circuits  Random Sequences  Binary Sequences  Cmos Analogue Integrated Circuits  Inductorless Analogue Equaliser  Low-frequency Equalisation Compensation  Lfeq  Low-frequency Channel Loss  Active Feedback Topology  Negative Capacitance Circuit  Data Jitter  Pseudorandom Binary Sequence  Cmos Technology  Loss 15 Db  Bit Rate 13 gBit  s  Size 65 Nm  Voltage 1  2 v  
Deferred partial compensation algorithm for view increment computing Journal article
Zou X.-X., Pan J.-H., Jia W.-J.. Deferred partial compensation algorithm for view increment computing[J]. Jisuanji Jicheng Zhizao Xitong/Computer Integrated Manufacturing Systems, CIMS, 2011, 17(5), 1024-1031.
Authors:  Zou X.-X.;  Pan J.-H.;  Jia W.-J.
Favorite |  | Submit date：2019/02/11
Algorithms  Asynchronous propagation  Data warehouses  Increment computing  Materialized view  Partial compensation