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Multi-layer SIW vertical transition and its applications in wideband crossover and monopulse comparator Journal article
Qiu, Lei Lei, Wu, Yueyang, Huang, Shengxiang, Deng, Lianwen, Ouyang, Zhao An, Zhu, Lei. Multi-layer SIW vertical transition and its applications in wideband crossover and monopulse comparator[J]. Engineering Science and Technology, an International Journal, 2024, 56, 101776.
Authors:  Qiu, Lei Lei;  Wu, Yueyang;  Huang, Shengxiang;  Deng, Lianwen;  Ouyang, Zhao An; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:5.1/4.8 | Submit date：2024/08/05
Crossover  Miniaturized  Monopulse Comparator  Substrate Integrated Waveguide (Siw)  Vertical Transition  Wideband  
A review of four types of comparators Conference paper
Shijie He, Yuyao Liu, Peiqi Lu. A review of four types of comparators[C], 2022.
Authors:  Shijie He;  Yuyao Liu;  Peiqi Lu
Favorite | TC[Scopus]:0 | Submit date：2023/03/06
Comparator  Decrease Noise  Epc  Fia  High Speed  Low Energy  
A New Nano Design for Implementation of a Digital Comparator Based on Quantum-Dot Cellular Automata Journal article
Gao, Mingming, Wang, Jinling, Fang, Shaojun, Nan, Jingchang, Daming, Li. A New Nano Design for Implementation of a Digital Comparator Based on Quantum-Dot Cellular Automata[J]. International Journal of Theoretical Physics, 2021, 60(7), 2358-2367.
Authors:  Gao, Mingming;  Wang, Jinling;  Fang, Shaojun;  Nan, Jingchang;  Daming, Li
Favorite | TC[WOS]:22 TC[Scopus]:19  IF:1.3/1.2 | Submit date：2021/12/08
Comparator  Coulombic Interaction  Molecules  Nanoscale  Nanotechnology  Quantum-dot Cellular Automata (Qca)  
A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery (BBCDR) Circuit in 28-nm CMOS Journal article
Zhao,Xiaoteng, Chen,Yong, Mak,Pui In, Martins,Rui P.. A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery (BBCDR) Circuit in 28-nm CMOS[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2021, 68(1), 89-102.
Authors:  Zhao,Xiaoteng;  Chen,Yong;  Mak,Pui In;  Martins,Rui P.
Favorite | TC[WOS]:21 TC[Scopus]:22  IF:5.2/4.5 | Submit date：2021/03/09
Bang- Bang Clock And Data Recovery (Bbcdr)  Bang-bang Phase Detector (Bbpd)  Cmos  Four- And Eight-level Pulse Amplitude Modulation (Pam-4/-8)  Half Rate  Hogge And alexAnder Pd  Jitter Tolerance (Jtol).  Jitter Transfer Function (Jtf)  Non-return-to-zero (Nrz)  Strongarm Comparator  
A 65.5-dB SNDR 8.1–11.1-nW ECG SAR ADC With Adaptive-Latching OSC-Based Comparator and DAC Calibration Journal article
Li,Kejin, Zhang,Wai Hong, Chen,Yun, Zhu,Yan, Chan,Chi Hang, Martins,Rui Paulo. A 65.5-dB SNDR 8.1–11.1-nW ECG SAR ADC With Adaptive-Latching OSC-Based Comparator and DAC Calibration[J]. IEEE Solid-State Circuits Letter, 2020, 3, 482-485.
Authors:  Li,Kejin;  Zhang,Wai Hong;  Chen,Yun;  Zhu,Yan;  Chan,Chi Hang; et al.
Favorite | TC[WOS]:1 TC[Scopus]:4 | Submit date：2022/01/25
Ecg Analog-to-digital Converter (Adc)  Lsb-first Algo-rithm  Osc-based Comparator  Calibration  
A 65.5-dB SNDR 8.1-11.1-nW ECG SAR ADC with Adaptive-Latching OSC-Based Comparator and DAC Calibration Journal article
Li,Kejin, Zhang,Wai Hong, Chen,Yun, Zhu,Yan, Chan,Chi Hang, Martins,Rui Paulo. A 65.5-dB SNDR 8.1-11.1-nW ECG SAR ADC with Adaptive-Latching OSC-Based Comparator and DAC Calibration[J]. IEEE Solid-State Circuits Letters, 2020, 3, 482-485.
Authors:  Li,Kejin;  Zhang,Wai Hong;  Chen,Yun;  Zhu,Yan;  Chan,Chi Hang; et al.
Favorite | TC[WOS]:1 TC[Scopus]:4 | Submit date：2021/03/09
Calibration  Ecg Analog-to-digital Converter (Adc)  Lsb-first Algorithm  Osc-based Comparator  
A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery Circuit (BBCDR) in 28-nm CMOS Conference paper
Xiaoteng Zhao, Yong Chen, Pui-In Mak, Rui P. Martins. A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery Circuit (BBCDR) in 28-nm CMOS[C]:IEEE, 2019, 229-232.
Authors:  Xiaoteng Zhao;  Yong Chen;  Pui-In Mak;  Rui P. Martins
Favorite | TC[WOS]:6 TC[Scopus]:7 | Submit date：2021/03/09
4-/8-level Pulse Amplitude Modulation (Pam-4/8)  Bang-bang Phase Detector (Bbpd)  Clock And Data Recovery (Cdr)  Half Rate  Non-return To Zero (Nrz)  Strongarm Comparator  Voltage-to-current (V/i) Converter  Xor  
Background Offset Calibration for Comparator Based on Temperature Drift Profile Journal article
Li,Xiaochao, Chan,Chi Hang, Zhang,Qi, Zhu,Yan, Martins,R. P.. Background Offset Calibration for Comparator Based on Temperature Drift Profile[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2019, 66(10), 1648-1652.
Authors:  Li,Xiaochao;  Chan,Chi Hang;  Zhang,Qi;  Zhu,Yan;  Martins,R. P.
Favorite | TC[WOS]:4 TC[Scopus]:7  IF:4.0/3.7 | Submit date：2021/03/09
Background Self-calibration  Offset Drift  Preamplifier Comparator  
An 11-bit 100-MS/s Pipelined-SAR ADC Reusing PVT-Stabilized Dynamic Comparator in 65-nm CMOS Journal article
Zhang, Jin, Ren, Xiaoqian, Liu, Shubin, Chan, Chi Hang, Zhu, Zhangming. An 11-bit 100-MS/s Pipelined-SAR ADC Reusing PVT-Stabilized Dynamic Comparator in 65-nm CMOS[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2019, 67(7), 1174-1178.
Authors:  Zhang, Jin;  Ren, Xiaoqian;  Liu, Shubin;  Chan, Chi Hang;  Zhu, Zhangming
Favorite | TC[WOS]:9 TC[Scopus]:18  IF:4.0/3.7 | Submit date：2021/12/06
Analog-to-digital Converter (Adc)  Full Dynamic Adc  Pipelined Successive-approximation-register (Sar)  Pvt-stabilized Dynamic Amplification  Reused Comparator  
A digital LDO with Co-SA logics and TSPC dynamic latches for fast transient response Journal article
Zhao,Lei, Lu,Yan, Martins,Rui P.. A digital LDO with Co-SA logics and TSPC dynamic latches for fast transient response[J]. IEEE Solid-State Circuits Letters, 2018, 1(6), 154-157.
Authors:  Zhao,Lei;  Lu,Yan;  Martins,Rui P.
Favorite | TC[WOS]:13 TC[Scopus]:16  IF:2.2/2.0 | Submit date：2021/03/09
Continuous-time Comparator  Digital Low-dropout Regulator (Dldo)  Dynamic Logic  Transient Response  True Single-phase Clock (Tspc) Latch