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Area-efficient ultra-wide-tuning-range ring oscillators in 65-nm complementary metal–oxide–semiconductor Journal article
Yang, Chaowei, Chen, Yong, Cheng, Kai, Stefano, Crovetti Paolo, Martins, Rui P., Mak, Pui In. Area-efficient ultra-wide-tuning-range ring oscillators in 65-nm complementary metal–oxide–semiconductor[J]. International Journal of Circuit Theory and Applications, 2024.
Authors:  Yang, Chaowei;  Chen, Yong;  Cheng, Kai;  Stefano, Crovetti Paolo;  Martins, Rui P.; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:1.8/1.7 | Submit date：2024/08/05
Clock And Data Recovery (Cdr)  Cmos Figure-of-merit (Fom)  Figure-of-merit With Tuning And Area (Fomta)  Figure-of-merit With Tuning Range (Fomt)  Flicker (1/f)  Noise Noise Transfer Phase Noise (Pn)  Phase-locked Loop (Pll)  Quality Factor Switched-capacitor Array (Sca)  Thermal Noise Transformer Tuning Range (Tr)  Ultra-wide-tuning-range Voltage-controlled Oscillator (Vco)  
A 95% Peak Efficiency Modified KY Converter With Improved Flying Capacitor Charging in DCM for IoT Applications Journal article
Pan,Caolei, Zeng,Wen Liang, Lam,Chi Seng, Sin,Sai Weng, Zhan,Chenchang, Martins,Rui P.. A 95% Peak Efficiency Modified KY Converter With Improved Flying Capacitor Charging in DCM for IoT Applications[J]. IEEE Journal of Solid-State Circuits, 2023, 58(11), 3219-3230.
Authors:  Pan,Caolei;  Zeng,Wen Liang;  Lam,Chi Seng;  Sin,Sai Weng;  Zhan,Chenchang; et al.
Favorite | TC[WOS]:3 TC[Scopus]:3  IF:4.6/5.6 | Submit date：2023/08/03
Adaptive Sizing  Clocked-feedback Resistor Network (Cfrn)  Discontinuous Conduction Mode (Dcm)  Double Clock Timing (Dct) Control  Modified Ky (m-Ky) Converter  Wide Load Range  
A 0.0035-mm20.42-pJ/bit 8-32-Gb/s Reference-Less CDR Incorporating Adaptively-Biased ChargeSharing Integrator, Alexander PFD, and 1-Tap DFE Conference paper
Zhang, Zhaoyu, Zhang, Zhao, Chen, Yong, Wang, Guoqing, Shen, Xinyu, Qi, Nan, Li, Guike, Yu, Shuangming, Liu, Jian, Wu, Nanjian, Liu, Liyuan. A 0.0035-mm20.42-pJ/bit 8-32-Gb/s Reference-Less CDR Incorporating Adaptively-Biased ChargeSharing Integrator, Alexander PFD, and 1-Tap DFE[C], New York, USA:IEEE, 2023, 177-180.
Authors:  Zhang, Zhaoyu;  Zhang, Zhao;  Chen, Yong;  Wang, Guoqing;  Shen, Xinyu; et al.
Favorite | TC[WOS]:0 TC[Scopus]:1 | Submit date：2024/02/22
Charge Sharing Integrator  Clock And Data Recovery (Cdr)  Cmos  Continuous-rate  Reference-less  
A 2.0-to-7.4-GHz 16-Phase Delay-Locked Loop With a Sub-0.6-ps Phase-Delay Error in 40-nm CMOS Journal article
Yang,Jian, Pan,Quan, Yin,Jun, Mak,Pui In. A 2.0-to-7.4-GHz 16-Phase Delay-Locked Loop With a Sub-0.6-ps Phase-Delay Error in 40-nm CMOS[J]. IEEE Transactions on Microwave Theory and Techniques, 2023, 71(8), 3596 - 3604.
Authors:  Yang,Jian;  Pan,Quan;  Yin,Jun;  Mak,Pui In
Favorite | TC[WOS]:4 TC[Scopus]:4  IF:4.1/4.2 | Submit date：2023/08/03
Charge Pump (Cp)  Clock Generator  Delay-locked Loop (Dll)  Locking Range  Multiphase Clock  Phase Accuracy  
Ring-VCO-based Phase-Locked Loops for Clock Generation – Design Considerations and State-of-the-Art Journal article
Shiheng Yang, Jun Yin, Yueduo Liu, Rongxin Bao, Zihao Zhu, Jiahui Lin, Qiang Li, Pui-In Mak, Rui P. Martins. Ring-VCO-based Phase-Locked Loops for Clock Generation – Design Considerations and State-of-the-Art[J]. Chip, 2023, 2(2), 1-10.
Authors:  Shiheng Yang;  Jun Yin;  Yueduo Liu;  Rongxin Bao;  Zihao Zhu; et al.
Favorite | TC[WOS]:1 TC[Scopus]:3 | Submit date：2023/08/19
Clock Generation, Ic Design, Phase-locked Loop (Pll), Frequency Synthesizer  
A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique Journal article
Wang,Lin, Chen,Yong, Yang,Chaowei, Zhao,Xiaoteng, Mak,Pui In, Maloberti,Franco, Martins,Rui P.. A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2023, 70(7), 2637-2650.
Authors:  Wang,Lin;  Chen,Yong;  Yang,Chaowei;  Zhao,Xiaoteng;  Mak,Pui In; et al.
Favorite | TC[WOS]:1 TC[Scopus]:4  IF:5.2/4.5 | Submit date：2023/08/03
Bang-bang Clock And Data Recovery (Bbcdr)  Wide Capture Range  Single Loop  Frequency Detector (Fd)  Hybrid Control Circuit (Hcc)  Deliberate Current Mismatch  Ring Oscillator (Ro)  R-2r Dac  Positive (Pnc)  Negative (Nnc) And Zero (Znc) Net Current  Cmos  Bang-bang Phase Detector (Bbpd)  
The enormous repetitive Antarctic krill genome reveals environmental adaptations and population insights Journal article
Shao, Changwei, Sun, Shuai, Liu, Kaiqiang, Wang, Jiahao, Li, Shuo, Liu, Qun, Deagle, Bruce E., Seim, Inge, Biscontin, Alberto, Wang, Qian, Liu, Xin, Kawaguchi, So, Liu, Yalin, Jarman, Simon, Wang, Yue, Wang, Hong Yan, Huang, Guodong, Hu, Jiang, Feng, Bo, De Pittà, Cristiano, Liu, Shanshan, Wang, Rui, Ma, Kailong, Ying, Yiping, Sales, Gabrielle, Sun, Tao, Wang, Xinliang, Zhang, Yaolei, Zhao, Yunxia, Pan, Shanshan, Hao, Xiancai, Wang, Yang, Xu, Jiakun, Yue, Bowen, Sun, Yanxu, Zhang, He, Xu, Mengyang, Liu, Yuyan, Jia, Xiaodong, Zhu, Jiancheng, Liu, Shufang, Ruan, Jue, Zhang, Guojie, Yang, Huanming, Xu, Xun, Wang, Jun, Zhao, Xianyong, Meyer, Bettina, Fan, Guangyi. The enormous repetitive Antarctic krill genome reveals environmental adaptations and population insights[J]. Cell, 2023, 186(6), 1279-1294.e19.
Authors:  Shao, Changwei;  Sun, Shuai;  Liu, Kaiqiang;  Wang, Jiahao;  Li, Shuo; et al.
Favorite | TC[WOS]:34 TC[Scopus]:36  IF:45.5/49.0 | Submit date：2023/04/03
Antarctic Krill (Euphausia Superba)  Chromosome-level Genome  Circadian Clock  Environmental Adaptation  Giant Genome Size  Population Demography  Population Differentiation  Repeat Expansions  
A 6-to-38Gb/s capture-range bang-bang clock and data recovery circuit with deliberate-current-mismatch frequency detection and interpolation-based multiphase clock generation Journal article
Wang, Lin, Chen, Yong, Yang, Chaowei, Zhou, Xionghui, Han, Mei, Stefano, Crovetti Paolo, Mak, Pui In, Martins, Rui P.. A 6-to-38Gb/s capture-range bang-bang clock and data recovery circuit with deliberate-current-mismatch frequency detection and interpolation-based multiphase clock generation[J]. International Journal of Circuit Theory and Applications, 2023, 51(5), 1988-2015.
Authors:  Wang, Lin;  Chen, Yong;  Yang, Chaowei;  Zhou, Xionghui;  Han, Mei; et al.
Favorite | TC[WOS]:1 TC[Scopus]:2  IF:1.8/1.7 | Submit date：2023/06/05
Bang-bang Clock And Data Recovery (Bbcdr)  Current Mismatch  Frequency Detector (Fd)  Hybrid Control Circuit (Hcc)  Phase Interpolator (Pi)  R-2r Digital-to-analog Converter (Dac)  Ring Oscillator (Ro)  Switched-capacitor (Sc) Array  Wide Capture Range  
A Crystal-Less Clock Generation Technique for Battery-Free Wireless Systems Journal article
Chang, Ziyi, Zhang, Yunshan, Yang, Changgui, Luo, Yuxuan, Du, Sijun, Chen, Yong, Zhao, Bo. A Crystal-Less Clock Generation Technique for Battery-Free Wireless Systems[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2022, 69(12), 4981-4992.
Authors:  Chang, Ziyi;  Zhang, Yunshan;  Yang, Changgui;  Luo, Yuxuan;  Du, Sijun; et al.
Favorite | TC[WOS]:1 TC[Scopus]:2  IF:5.2/4.5 | Submit date：2023/01/30
Battery-free  Clock Generator  Wireless Power Transfer (Wpt)  Injection Locking  Inter-modulation  
A 28-Gb/s 13.8-mW Half-Rate Bang-Bang Clock and Data Recovery Circuit Using Return-to-Zero-Based Symmetrical Bang-Bang Phase Detector Conference paper
Ge, Xinyi, Chen, Yong, Wang, Lin, Qi, Nan, Mak, Pui In, Martins, Rui P.. A 28-Gb/s 13.8-mW Half-Rate Bang-Bang Clock and Data Recovery Circuit Using Return-to-Zero-Based Symmetrical Bang-Bang Phase Detector[C]:IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA, 2022.
Authors:  Ge, Xinyi;  Chen, Yong;  Wang, Lin;  Qi, Nan;  Mak, Pui In; et al.
Favorite | TC[WOS]:4 TC[Scopus]:5 | Submit date：2023/01/30
Bang-bang Phase Detector (Bbpd)  Charge Steering  Clock And Data Recovery (Cdr)  Cmos  Half Rate  Non- Return-to-zero (Nrz)  Quadrature Voltage-controlled Oscillator (Qvco)  Return-to-zero (Rz)  Rz-to-nrz Converter