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Analyses Concerning the Phase Noise and Nonlinear Behavior of the Charge-Sharing Integrator-Based Hybrid PLL Journal article
Song, Jingrun, Yang, Xinyu, Liu, Jiaxu, Liu, Yueduo, Zhu, Zihao, Han, Zhengxuan, Zhang, Zehao, Liu, Jiaxin, Zhang, Hongshuai, Yin, Jun, Mak, Pui In, Yang, Shiheng. Analyses Concerning the Phase Noise and Nonlinear Behavior of the Charge-Sharing Integrator-Based Hybrid PLL[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2024.
Authors:  Song, Jingrun;  Yang, Xinyu;  Liu, Jiaxu;  Liu, Yueduo;  Zhu, Zihao; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:5.2/4.5 | Submit date：2024/12/26
Charge-sharing Integrator  Hybrid Pll (hPll)  Digital Pll (dPll)  Digitally Controlled Oscillator (Dco)  Jitter  Multi-rate  Nonlinearity  Phase Noise (Pn)  Prediction  Spur  Spectrum  
A 0.0035-mm20.42-pJ/bit 8-32-Gb/s Reference-Less CDR Incorporating Adaptively-Biased ChargeSharing Integrator, Alexander PFD, and 1-Tap DFE Conference paper
Zhang, Zhaoyu, Zhang, Zhao, Chen, Yong, Wang, Guoqing, Shen, Xinyu, Qi, Nan, Li, Guike, Yu, Shuangming, Liu, Jian, Wu, Nanjian, Liu, Liyuan. A 0.0035-mm20.42-pJ/bit 8-32-Gb/s Reference-Less CDR Incorporating Adaptively-Biased ChargeSharing Integrator, Alexander PFD, and 1-Tap DFE[C], New York, USA:IEEE, 2023, 177-180.
Authors:  Zhang, Zhaoyu;  Zhang, Zhao;  Chen, Yong;  Wang, Guoqing;  Shen, Xinyu; et al.
Favorite | TC[WOS]:1 TC[Scopus]:2 | Submit date：2024/02/22
Charge Sharing Integrator  Clock And Data Recovery (Cdr)  Cmos  Continuous-rate  Reference-less  
Arithmetic Progression Switched-Capacitor DC-DC Converter Topology With Soft VCR Transitions and Quasi-Symmetric Two-Phase Charge Delivery Journal article
Yang Jiang, Man Kay Law, Pui In Mak, Rui P. Martins. Arithmetic Progression Switched-Capacitor DC-DC Converter Topology With Soft VCR Transitions and Quasi-Symmetric Two-Phase Charge Delivery[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2022, 57(10), 2919-2933.
Authors:  Yang Jiang;  Man Kay Law;  Pui In Mak;  Rui P. Martins
Favorite | TC[WOS]:7 TC[Scopus]:10  IF:4.6/5.6 | Submit date：2022/05/17
Bootstrapping Driver  Capacitors  Charge Sharing  Dc-dc Converter  Reconfigurable  Soft Transition  Steady-state  Switched-capacitor (Sc)  Switches  Topology  Topology  Video Recording  Voltage  Voltage Control  Voltage Conversion Ratio (Vcr).  
A 600-µm2 Ring-VCO-Based Type-II Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS Journal article
Yang, Shiheng, Yin, Jun, Xu, Tailong, Yi, Taimo, Mak, Pui-In, Li, Qiang, Martins, Rui P.. A 600-µm2 Ring-VCO-Based Type-II Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2021, 68(9), 3108-3112.
Authors:  Yang, Shiheng;  Yin, Jun;  Xu, Tailong;  Yi, Taimo;  Mak, Pui-In; et al.
Favorite | TC[WOS]:7 TC[Scopus]:8  IF:4.0/3.7 | Submit date：2022/08/19
Area  Analog Phase-locked Loop (Pll)  Cmos  Charge-sharing Integrator  Digital Pll  Hybrid Pll  Integrator  Integer-n  Jitter  Ring Oscillator  Ultra-low Power  
A 600-µm2 Ring-VCO-Based Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS Journal article
Yang, Shiheng, Yin, Jun, Xu, Tailong, Yi, Taimo, Mak, Pui-In, Li, Qiang, Martins, Rui P.. A 600-µm2 Ring-VCO-Based Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2021, 68(9), 3108 - 3112.
Authors:  Yang, Shiheng;  Yin, Jun;  Xu, Tailong;  Yi, Taimo;  Mak, Pui-In; et al.
Favorite | TC[WOS]:7 TC[Scopus]:8  IF:4.0/3.7 | Submit date：2022/01/25
Area  Analog Phase-locked Loop (Pll)  Cmos  Charge-sharing Integrator  Digital Pll  Hybrid Pll  Integrator  Integer-n  Jitter  Ring Oscillator  Ultra-low Power  
A 600-μm² Ring-VCO-Based Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS Journal article
Yang, Shiheng, Yin, Jun, Xu, Tailong, Yi, Taimo, Mak, Pui In, Li, Qiang, Martins, Rui P.. A 600-μm² Ring-VCO-Based Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2021, 68(9), 3108-3112.
Authors:  Yang, Shiheng;  Yin, Jun;  Xu, Tailong;  Yi, Taimo;  Mak, Pui In; et al.
Favorite | TC[WOS]:7 TC[Scopus]:8  IF:4.0/3.7 | Submit date：2021/09/20
Analog Phase-locked Loop (Pll)  Area  Charge-sharing Integrator  Cmos  Digital Pll  Hybrid Pll  Integer-n  Integrator  Jitter  Ring Oscillator  Ultra-low Power  
Algebraic Series-Parallel-Based Switched-Capacitor DC-DC Boost Converter with Wide Input Voltage Range and Enhanced Power Density Journal article
Jiang,Yang, Law,Man Kay, Chen,Zhiyuan, Mak,Pui In, Martins,Rui P.. Algebraic Series-Parallel-Based Switched-Capacitor DC-DC Boost Converter with Wide Input Voltage Range and Enhanced Power Density[J]. IEEE Journal of Solid-State Circuits, 2019, 54(11), 3118-3134.
Authors:  Jiang,Yang;  Law,Man Kay;  Chen,Zhiyuan;  Mak,Pui In;  Martins,Rui P.
Favorite | TC[WOS]:26 TC[Scopus]:34  IF:4.6/5.6 | Submit date：2021/03/09
Algebraic  Boost Converter  Charge Sharing Loss  Dc-dc  Parasitic Loss  Power Density  Rational  Series-parallel (Sp)  Switched-capacitor (Sc)  Voltage Conversion Ratio (Vcr)