×
验证码:
换一张
Forgotten Password?
Stay signed in
Login With UMPASS
English
|
繁體
Login With UMPASS
Log In
ALL
ORCID
TI
AU
PY
SU
KW
TY
JN
DA
IN
PB
FP
ST
SM
Study Hall
Image search
Paste the image URL
Home
Faculties & Institutes
Scholars
Publications
Subjects
Statistics
News
Search in the results
Faculties & Institutes
THE STATE KEY LA... [1]
INSTITUTE OF MIC... [1]
Faculty of Scien... [1]
Authors
MAK PUI IN [1]
Document Type
Journal article [1]
Date Issued
2018 [1]
Language
英語English [1]
Source Publication
IEEE Transaction... [1]
Indexed By
SCIE [1]
Funding Organization
Funding Project
×
Knowledge Map
UM
Start a Submission
Submissions
Unclaimed
Claimed
Attach Fulltext
Bookmarks
Browse/Search Results:
1-1 of 1
Help
Selected(
0
)
Clear
Items/Page:
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
Sort:
Select
Issue Date Ascending
Issue Date Descending
Journal Impact Factor Ascending
Journal Impact Factor Descending
WOS Cited Times Ascending
WOS Cited Times Descending
Submit date Ascending
Submit date Descending
Title Ascending
Title Descending
Author Ascending
Author Descending
A hardware-efficient feedback polynomial topology for dpd linearization of power amplifiers: Theory and FPGA validation
Journal article
Chak-Fong Cheang, Pui-In Mak, Rui P. Martins. A hardware-efficient feedback polynomial topology for dpd linearization of power amplifiers: Theory and FPGA validation[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2018, 65(9), 2889-2902.
Authors:
Chak-Fong Cheang
;
Pui-In Mak
;
Rui P. Martins
Favorite
|
TC[WOS]:
13
TC[Scopus]:
16
|
Submit date：2019/02/11
Carrier-aggregation
Digital Predistortion (Dpd)
Field-programmable Gate Array (Fpga)
Identification
Power Amplifier (Pa)
Recursive Least Square (Rls)
