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THE STATE KEY LA... [1]
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MAK PUI IN [1]
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Journal article [1]
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2021 [1]
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A 3.3-GHz Integer N-Type-II Sub-Sampling PLL Using a BFSK-Suppressed Push-Pull SS-PD and a Fast-Locking FLL Achieving -82.2-dBc REF Spur and -255-dB FOM
Journal article
Yang, Zunsong, Chen, Yong, Yuan, Jia, Mak, Pui In, Martins, Rui P.. A 3.3-GHz Integer N-Type-II Sub-Sampling PLL Using a BFSK-Suppressed Push-Pull SS-PD and a Fast-Locking FLL Achieving -82.2-dBc REF Spur and -255-dB FOM[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2021, 30(2), 238-242.
Authors:
Yang, Zunsong
;
Chen, Yong
;
Yuan, Jia
;
Mak, Pui In
;
Martins, Rui P.
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TC[WOS]:
21
TC[Scopus]:
22
IF:
2.8
/
2.8
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Submit date：2022/03/04
Binary Frequency Shift Keying (Bfsk)
Frequency-locked Loop (Fll)
Integer-n
Phase Detector (Pd)
Phase Noise (Pn)
Phase-locked Loop (Pll)
Push-pull
Reference (Ref) Spur
Sub-sampling (Ss)
Voltage-controlled Oscillator (Vco)
