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Analysis and verification of jitter in bang-bang clock and data recovery circuit with a second-order loop filter
Journal article
Ge,Xinyi, Chen,Yong, Zhao,Xiaoteng, Mak,Pui In, Martins,Rui P.. Analysis and verification of jitter in bang-bang clock and data recovery circuit with a second-order loop filter[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019, 27(10), 2223-2236.
Authors:
Ge,Xinyi
;
Chen,Yong
;
Zhao,Xiaoteng
;
Mak,Pui In
;
Martins,Rui P.
Favorite
|
TC[WOS]:
19
TC[Scopus]:
19
IF:
2.8
/
2.8
|
Submit date:2021/03/09
Bang-bang Clock And Data Recovery (Bbcdr)
Bang-bang Phase Detector (Bbpd)
Binary
Fourier Series
Jitter Generation (Jgen)
Jitter Tolerance (Jtol)
Jitter Transfer Function (Jtf)
Linear Phase Detector
Loop Filter (Lf)
Sinking Area
Separable and Reversible Data Hiding in Encrypted Images Using Parametric Binary Tree Labeling
Journal article
Yi, Shuang, Zhou, Yicong. Separable and Reversible Data Hiding in Encrypted Images Using Parametric Binary Tree Labeling[J]. IEEE TRANSACTIONS ON MULTIMEDIA, 2019, 21(1), 51-64.
Authors:
Yi, Shuang
;
Zhou, Yicong
Favorite
|
TC[WOS]:
145
TC[Scopus]:
183
IF:
8.4
/
8.0
|
Submit date:2019/01/17
Reversible Data Hiding
Encrypted Images
Parametric Binary Tree Labeling Scheme
Privacy Protection
0.058 mm(2) 13 Gbit/s inductorless analogue equaliser with low-frequency equalisation compensating 15 dB channel loss
Journal article
Balachandran, Arya, Chen, Yong, Choi, Pilsoon, Boon, Chirn Chye. 0.058 mm(2) 13 Gbit/s inductorless analogue equaliser with low-frequency equalisation compensating 15 dB channel loss[J]. ELECTRONICS LETTERS, 2018, 54(2).
Authors:
Balachandran, Arya
;
Chen, Yong
;
Choi, Pilsoon
;
Boon, Chirn Chye
Favorite
|
TC[WOS]:
6
TC[Scopus]:
9
IF:
0.7
/
0.9
|
Submit date:2018/10/30
Equalisers
Circuit Feedback
Analogue Circuits
Random Sequences
Binary Sequences
Cmos Analogue Integrated Circuits
Inductorless Analogue Equaliser
Low-frequency Equalisation Compensation
Lfeq
Low-frequency Channel Loss
Active Feedback Topology
Negative Capacitance Circuit
Data Jitter
Pseudorandom Binary Sequence
Cmos Technology
Loss 15 Db
Bit Rate 13 gBit
s
Size 65 Nm
Voltage 1
2 v
Binary-block embedding for reversible data hiding in encrypted images
Journal article
Yi, Shuang, Zhou, Yicong. Binary-block embedding for reversible data hiding in encrypted images[J]. Signal Processing, 2017, 133, 40-51.
Authors:
Yi, Shuang
;
Zhou, Yicong
Favorite
|
TC[WOS]:
121
TC[Scopus]:
151
IF:
3.4
/
3.8
|
Submit date:2018/10/30
Binary-block Embedding (Bee)
Reversible Data Hiding
Image Encryption
Encrypted Domain
Logit tree models for discrete choice data with application to advice-seeking preferences among Chinese Christians
Journal article
Yu, P. L. H., Lee, P. H., Cheung, S. F., Lau, E. Y. Y., Mok, S. Y., Hui, C. H.. Logit tree models for discrete choice data with application to advice-seeking preferences among Chinese Christians[J]. Computational Statistics, 2016, 31, 799-827.
Authors:
Yu, P. L. H.
;
Lee, P. H.
;
Cheung, S. F.
;
Lau, E. Y. Y.
;
Mok, S. Y.
; et al.
Favorite
|
TC[WOS]:
7
TC[Scopus]:
8
IF:
1.0
/
1.3
|
Submit date:2022/05/04
Binary Data
Decision Tree
Multinomial Data
Ranking Data
Variable Selection