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A 12-Bit 50 MS/s Split-CDAC-Based SAR ADC Integrating Input Programmable Gain Amplifier and Reference Voltage Buffer Journal article
Xu, Zhuofan, Hu, Biao, Wu, Tianxiang, Yao, Yuting, Chen, Yong, Ren, Junyan, Ma, Shunli. A 12-Bit 50 MS/s Split-CDAC-Based SAR ADC Integrating Input Programmable Gain Amplifier and Reference Voltage Buffer[J]. Electronics (Switzerland), 2022, 11(12).
Authors:  Xu, Zhuofan;  Hu, Biao;  Wu, Tianxiang;  Yao, Yuting;  Chen, Yong; et al.
Favorite | TC[WOS]:7 TC[Scopus]:10  IF:2.6/2.6 | Submit date：2022/08/02
Split Cdac  Asynchronous Sar Adc  Input Pga  Rv-buffer  
A 6.94-fJ/Conversion-Step 12-bit 100-MS/s Asynchronous SAR ADC Exploiting Split-CDAC in 65-nm CMOS Journal article
Li, Manxin, Yao, Yuting, Hu, Biao, Wei, Jipeng, Chen, Yong, Ma, Shunli, Ye, Fan, Ren, Junyan. A 6.94-fJ/Conversion-Step 12-bit 100-MS/s Asynchronous SAR ADC Exploiting Split-CDAC in 65-nm CMOS[J]. IEEE Access, 2021, 9, 77545-77554.
Authors:  Li, Manxin;  Yao, Yuting;  Hu, Biao;  Wei, Jipeng;  Chen, Yong; et al.
Favorite | TC[WOS]:12 TC[Scopus]:18  IF:3.4/3.7 | Submit date：2021/10/28
Successive Approximation Register (Sar) Analog-to-digital Converter (Adc)  Cmos  Splitcdac  Customized Unit Capacitor  Asynchronous Logic  Figure-of-merit (Fom)  
A 4.8-bit ENOB 5-bit 500MS/s binary-search ADC with minimized number of comparators Conference paper
Wong S.-S., Chio U.-F., Chan C.-H., Choi H.-L., Sin S.-W., Seng-Pan U., Martins R.P.. A 4.8-bit ENOB 5-bit 500MS/s binary-search ADC with minimized number of comparators[C], 2011, 73-76.
Authors:  Wong S.-S.;  Chio U.-F.;  Chan C.-H.;  Choi H.-L.;  Sin S.-W.; et al.
Favorite | TC[Scopus]:22 | Submit date：2019/02/11
Analog-to-digital Converter (Adc)  Asynchronous Binary-search Adc  Flash Adc  Sar Adc