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A Compact Sub-nW/kHz Relaxation Oscillator Using a Negative-Offset Comparator With Chopping and Piecewise Charge-Acceleration in 28-nm CMOS Journal article
Liu, Yueduo, Zhu, Zihao, Bao, Rongxin, Lin, Jiahui, Yin, Jun, Li, Qiang, Mak, Pui-In, Yang, Shiheng. A Compact Sub-nW/kHz Relaxation Oscillator Using a Negative-Offset Comparator With Chopping and Piecewise Charge-Acceleration in 28-nm CMOS[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2023, 71(2), 515-525.
Authors:  Liu, Yueduo;  Zhu, Zihao;  Bao, Rongxin;  Lin, Jiahui;  Yin, Jun; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:5.2/4.5 | Submit date：2024/03/13
Allan Deviation  Cmos  Energy Efficiency  Internet Of Things (Iot)  Rc Oscillator  Relaxation Oscillator  Small Area  Temperature Stability  Timing Accuracy  Ultra-low-power  
Efficacy and Efficiency of Laws: Some Thoughts on the Conceptual Underpinnings and Assessing Cybersecurity Laws in the Greater Bay Area Economic Region of Southern China Journal article
Ramaswamy, M.P.. Efficacy and Efficiency of Laws: Some Thoughts on the Conceptual Underpinnings and Assessing Cybersecurity Laws in the Greater Bay Area Economic Region of Southern China[J]. Fiat Iustitia, 2020, 163-175.
Authors:  Ramaswamy, M.P.
Favorite |  | Submit date：2022/08/24
Efficiency  Efficacy  Norms  Assessment  Cyber-security  Greater Bay Area  
Efficacy and Efficiency of Laws: Some Thoughts on the Conceptual Underpinnings and Assessing Cybersecurity Laws in the Greater Bay Area Economic Region of Southern China Journal article
Ramaswamy, M.P.. Efficacy and Efficiency of Laws: Some Thoughts on the Conceptual Underpinnings and Assessing Cybersecurity Laws in the Greater Bay Area Economic Region of Southern China[J]. Fiat Iustitia, 2020, 163-175.
Authors:  Ramaswamy, M.P.
Favorite |  | Submit date：2022/08/24
Efficiency  Efficacy  Norms  Assessment  Cyber-security  Greater Bay Area  
A 2.56mW 40MHz-Bandwidth 75dB-SNDR Partial- Interleaving SAR-Assisted NS Pipeline ADC With Background Inter-Stage Offset Calibration Conference paper
Song, Y., Zhu, Y., Chan, C. H., Martins, R. P.. A 2.56mW 40MHz-Bandwidth 75dB-SNDR Partial- Interleaving SAR-Assisted NS Pipeline ADC With Background Inter-Stage Offset Calibration[C], 2020.
Authors:  Song, Y.;  Zhu, Y.;  Chan, C. H.;  Martins, R. P.
Favorite |  | Submit date：2022/01/25
analogue-digital conversion  calibration  CMOS digital integrated circuits  digital-analogue conversion  low-power electronics  preamplifiers  background inter-stage offset calibration  noise-shaping SAR hybrid architecture  NS-SAR  SNDR  power-hungry preamplifiers  low-noise targets  Schreier FoM  0-1 MASH SDM  pipeline-SAR structure  single-channel ADC  power-hungry residue amplifier  ADC power  area-hungry bit weight calibration  dynamic amplifier  pipeline operation  power efficiency  partial interleaving structu  
Nested-Current-Mirror Rail-to-Rail-Output Single-Stage Amplifier with Enhancements of DC Gain, GBW and Slew Rate Journal article
Zushu Yan, Pui-In Mak, Man-Kay Law, Rui P. Martins, Franco Maloberti. Nested-Current-Mirror Rail-to-Rail-Output Single-Stage Amplifier with Enhancements of DC Gain, GBW and Slew Rate[J]. IEEE Journal of Solid-State Circuits, 2015, 50(10), 2353-2366.
Authors:  Zushu Yan;  Pui-In Mak;  Man-Kay Law;  Rui P. Martins;  Franco Maloberti
Favorite | TC[WOS]:61 TC[Scopus]:67 | Submit date：2019/02/11
Area Efficiency  Cmos  Current Mirror  Dc Gain  Differential-pair (Dp) Amplifier  Frequency Compensation  Gain-bandwidth Product (Gbw)  Low Temperature Polysilicon Lcd  Multi-stage Amplifier  Nested Current Mirror  Rail-to-rail Output Swing  Single-stage Amplifier  Slew Rate (Sr)  Stability