×
验证码:
换一张
Forgotten Password?
Stay signed in
Login With UMPASS
English
|
繁體
Login With UMPASS
Log In
ALL
ORCID
TI
AU
PY
SU
KW
TY
JN
DA
IN
PB
FP
ST
SM
Study Hall
Image search
Paste the image URL
Home
Faculties & Institutes
Scholars
Publications
Subjects
Statistics
News
Search in the results
Faculties & Institutes
INSTITUTE OF MIC... [3]
Faculty of Scien... [3]
Authors
RUI PAULO DA SIL... [1]
U SENG PAN [1]
SIN SAI WENG [1]
LAM CHI SENG [1]
ZHU YAN [1]
Document Type
Journal article [3]
Date Issued
2020 [1]
2018 [2]
Language
英語English [3]
Source Publication
IEEE TRANSACTION... [2]
IEEE TRANSACTION... [1]
Indexed By
SCIE [3]
EI [1]
Funding Organization
Funding Project
×
Knowledge Map
UM
Start a Submission
Submissions
Unclaimed
Claimed
Attach Fulltext
Bookmarks
Browse/Search Results:
1-3 of 3
Help
Selected(
0
)
Clear
Items/Page:
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
Sort:
Select
Journal Impact Factor Ascending
Journal Impact Factor Descending
Title Ascending
Title Descending
Author Ascending
Author Descending
Issue Date Ascending
Issue Date Descending
WOS Cited Times Ascending
WOS Cited Times Descending
Submit date Ascending
Submit date Descending
LDO-Free Power Management System: A 10-bit Pipelined ADC Directly Powered by Inductor-Based Boost Converter with Ripple Calibration
Journal article
Wang,Hanyu, Sin,Sai Weng, Lam,Chi Seng, Maloberti,Franco, Martins,Rui Paulo. LDO-Free Power Management System: A 10-bit Pipelined ADC Directly Powered by Inductor-Based Boost Converter with Ripple Calibration[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2020, 67(12), 4174-4186.
Authors:
Wang,Hanyu
;
Sin,Sai Weng
;
Lam,Chi Seng
;
Maloberti,Franco
;
Martins,Rui Paulo
Favorite
|
TC[WOS]:
6
TC[Scopus]:
8
IF:
5.2
/
4.5
|
Submit date:2021/03/04
Power Management
Switching-mode Power Converters
Boost Dc-dc Converters
Analog-to-digital Converters (Adcs)
Pipelined Adc
Ripple Calibration
Gain Error Calibrations for Two-Step ADCs: Optimizations Either in Accuracy or Chip Area
Journal article
Wang, Guan Cheng, Zhu, Yan, Chan, Chi-Hang, Seng-Pan, U., Martins, Rui P.. Gain Error Calibrations for Two-Step ADCs: Optimizations Either in Accuracy or Chip Area[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2018, 26(11), 2279-2289.
Authors:
Wang, Guan Cheng
;
Zhu, Yan
;
Chan, Chi-Hang
;
Seng-Pan, U.
;
Martins, Rui P.
Favorite
|
TC[WOS]:
2
TC[Scopus]:
2
IF:
2.8
/
2.8
|
Submit date:2019/01/17
Bridge Digital-to-analog Converter (Dac)
Gain Error Calibration
Successive Approximation Register (Sar)
Analog-to-digital Converters (Adcs)
Testing Signal Generation (Tsg)
A 16-mW 1-GS/s With 49.6-dB SNDR TI-SAR ADC for Software-Defined Radio in 65-nm CMOS
Journal article
Qiu, Lei, Tang, Kai, Zheng, Yuanjin, Siek, Liter, Zhu, Yan, U, Seng-Pan. A 16-mW 1-GS/s With 49.6-dB SNDR TI-SAR ADC for Software-Defined Radio in 65-nm CMOS[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2018, 26(3), 572-583.
Authors:
Qiu, Lei
;
Tang, Kai
;
Zheng, Yuanjin
;
Siek, Liter
;
Zhu, Yan
; et al.
Favorite
|
TC[WOS]:
15
TC[Scopus]:
16
IF:
2.8
/
2.8
|
Submit date:2018/10/30
Digital Background Calibration
Subradix-2
Successive Pproximation Register (Sar) Analog-to-digital Converters (Adcs)
Time Interleaved (Ti)
Time Skew