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An ELDC-Free 4th-Order CT SDM Facilitated by 2nd-Order NS CT-SAR and AC-Coupled Negative-R Journal article
Xu, Zixuan, Xing, Kai, Zhu, Yan, Martins, Rui P., Chan, Chi Hang. An ELDC-Free 4th-Order CT SDM Facilitated by 2nd-Order NS CT-SAR and AC-Coupled Negative-R[J]. IEEE Journal of Solid-State Circuits, 2024, 59(3), 753-764.
Authors:  Xu, Zixuan;  Xing, Kai;  Zhu, Yan;  Martins, Rui P.;  Chan, Chi Hang
Favorite | TC[WOS]:1 TC[Scopus]:0  IF:4.6/5.6 | Submit date：2024/04/02
Ac-coupled Negative-r  Analog-to-digital Conversion (Adc)  Continuous-time Sigma-delta Modulator (Ct Sdm)  Noise-shaping Continuous Time Successive-approximation Register (Ns Ct-sar)  
A 240 µW 17 bit ENOB ∆Σ modulator using 2nd-order noise-shaped integrating quantizer Journal article
Wang, Kunyu, Xu, Wenjing, Zhang, Chengbin, Law, Man Kay, Zhou, Li, Chen, Ming, Chen, Jie. A 240 µW 17 bit ENOB ∆Σ modulator using 2nd-order noise-shaped integrating quantizer[J]. IEICE Electronics Express, 2022, 19(5), 1-6.
Authors:  Wang, Kunyu;  Xu, Wenjing;  Zhang, Chengbin;  Law, Man Kay;  Zhou, Li; et al.
Favorite | TC[WOS]:1 TC[Scopus]:0  IF:0.8/0.7 | Submit date：2022/05/13
Analog-to-digital Conversion  Noise Enhancement Circuit  Noise-shaping Quantizer  ∆σ Modulator  
A Single-Opamp Third Order CT ΔΣ Modulator With SAB-ELD-Merged Integrator and Three-Stage Hybrid Compensation Opamp Journal article
Xing, K., Wang, W., Zhu, Y., Chan, C. H., Martins, R. P.. A Single-Opamp Third Order CT ΔΣ Modulator With SAB-ELD-Merged Integrator and Three-Stage Hybrid Compensation Opamp[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2022, 64-74.
Authors:  Xing, K.;  Wang, W.;  Zhu, Y.;  Chan, C. H.;  Martins, R. P.
Favorite |   IF:5.2/4.5 | Submit date：2023/08/31
Analog-to-digital conversion (ADC)  continuous-time delta-sigma modulator (CTDSM)  SAB-ELD- merged integrator  three-stage Opamp  preliminary sampling and quantization (PSQ) technique  high-speed noise-shaping SAR (NS-SAR)  
A Single-Opamp Third Order CT Δ Σ Modulator With SAB-ELD-Merged Integrator and Three-Stage Hybrid Compensation Opamp Journal article
Xing, Kai, Wang, Wei, Zhu, Yan, Chan, Chi Hang, Martins, Rui P.. A Single-Opamp Third Order CT Δ Σ Modulator With SAB-ELD-Merged Integrator and Three-Stage Hybrid Compensation Opamp[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2022, 69(1), 64-74.
Authors:  Xing, Kai;  Wang, Wei;  Zhu, Yan;  Chan, Chi Hang;  Martins, Rui P.
Favorite | TC[WOS]:5 TC[Scopus]:5  IF:5.2/4.5 | Submit date：2021/09/20
Analog-to-digital Conversion (Adc)  Continuous-time Delta-sigma Modulator (Ctdsm)  Gain  High-speed Noise-shaping Sar (ns-Sar).  Loading  Low-frequency Noise  Modulation  Preliminary Sampling And Quantization (Psq) Technique  Quantization (Signal)  Sab-eld-merged Integrator  Three-stage Opamp  Topology  Wideband  
Revisiting the Frontiers of Analog and Mixed-Signal Integrated Circuits Architectures and Techniques towards the future Internet of Everything (IoE) Applications Journal article
Rui P. Martins, Pui-In Mak, Sai-Weng Sin, Man-Kay Law, Yan Zhu, Yan Lu, Jun Yin, Chi-Hang Chan, Yong Chen, Ka-Fai Un, Mo Huang, Minglei Zhang, Yang Jiang, Wei-Han Yu. Revisiting the Frontiers of Analog and Mixed-Signal Integrated Circuits Architectures and Techniques towards the future Internet of Everything (IoE) Applications[J]. Foundations and Trends® in Integrated Circuits and Systems, 2021, 1(2-3), 72-216.
Authors:  Rui P. Martins;  Pui-In Mak;  Sai-Weng Sin;  Man-Kay Law;  Yan Zhu; et al.
Adobe PDF | Favorite |  | Submit date：2022/08/30
Analog-to-digital Converters, Mixed-signal Circuits And Systems, Rf Circuits, Mm-wave Integrated Circuits, Wireless Circuits, Wireline Circuits, Data Converters, Analog-to-digital Converters, Sensors, Analog-to-digital Conversion  
A 3.3-GS/s 6-b Fully Dynamic Pipelined ADC With Linearized Dynamic Amplifier Journal article
Zihao Zheng, Lai Wei, Jorge Lagos, Ewout Martens, Yan Zhu, Chi Hang Chan, Jan Craninckx, Rui P. Martins. A 3.3-GS/s 6-b Fully Dynamic Pipelined ADC With Linearized Dynamic Amplifier[J]. IEEE Journal of Solid-State Circuits, 2021.
Authors:  Zihao Zheng;  Lai Wei;  Jorge Lagos;  Ewout Martens;  Yan Zhu; et al.
Favorite | TC[WOS]:8 TC[Scopus]:9  IF:4.6/5.6 | Submit date：2021/09/20
Analog-to-digital Conversion  Calibration  Calibration  Dynamic Amplifier (Da)  Hardware  Linearity  Linearization Technique  Pipeline Processing  Pipelined Analog-to-digital Converter (Adc).  Quantization (Signal)  Signal Resolution  System-on-chip  
A 100-MHz BW 72.6-dB-SNDR CT ΔΣ Modulator Utilizing Preliminary Sampling and Quantization Journal article
Wang,Wei, Chan,Chi Hang, Zhu,Yan, Martins,Rui P.. A 100-MHz BW 72.6-dB-SNDR CT ΔΣ Modulator Utilizing Preliminary Sampling and Quantization[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2020, 55(6), 1588-1598.
Authors:  Wang,Wei;  Chan,Chi Hang;  Zhu,Yan;  Martins,Rui P.
Favorite | TC[WOS]:13 TC[Scopus]:15  IF:4.6/5.6 | Submit date：2020/12/04
Analog-to-digital Conversion (Adc)  Continuous-time Delta-sigma Modulator (Ct-dsm)  Preliminary Sampling And Quantization (Psq) Technique  Single Amplifier Biquad (Sab)  Successiveapproximation-register (Sar) Architecture-based Quantizer (Qtz)  
A 14-Bit Split-Pipeline ADC with Self-Adjusted Opamp-Sharing Duty-Cycle and Bias Current Journal article
Mao J., Guo M., Sin S.-W., Martins R.P.. A 14-Bit Split-Pipeline ADC with Self-Adjusted Opamp-Sharing Duty-Cycle and Bias Current[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2018, 65(10), 1380-1384.
Authors:  Mao J.;  Guo M.;  Sin S.-W.;  Martins R.P.
Favorite | TC[WOS]:8 TC[Scopus]:10 | Submit date：2019/02/11
Analog-to-digital Conversion  Digital Background Calibration  Opamp-sharing Technique  Pipelined Adc  Split Adc  
A 5.35-mW 10-MHz Single-Opamp Third-Order CT Δ\Σ Modulator with CTC Amplifier and Adaptive Latch DAC Driver in 65-nm CMOS Journal article
Wang,Wei, Zhu,Yan, Chan,Chi Hang, Martins,Rui Paulo. A 5.35-mW 10-MHz Single-Opamp Third-Order CT Δ\Σ Modulator with CTC Amplifier and Adaptive Latch DAC Driver in 65-nm CMOS[J]. IEEE Journal of Solid-State Circuits, 2018, 53(10), 2783-2794.
Authors:  Wang,Wei;  Zhu,Yan;  Chan,Chi Hang;  Martins,Rui Paulo
Favorite | TC[WOS]:11 TC[Scopus]:13 | Submit date：2019/08/22
Analog-to-digital Conversion (Adc)  Continuous-time (Ct) Delta-sigma Modulator  Dac Driver  Passive Integrator  Single Amplifier Biquad (Sab)  
A 14-Bit Split-Pipeline ADC With Self-Adjusted Opamp-Sharing Duty-Cycle and Bias Current Journal article
Mao, Jiaji, Guo, Mingqiang, Sin, Sai-Weng, Martins, Rui Paulo. A 14-Bit Split-Pipeline ADC With Self-Adjusted Opamp-Sharing Duty-Cycle and Bias Current[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2018, 65(10), 1380-1384.
Authors:  Mao, Jiaji;  Guo, Mingqiang;  Sin, Sai-Weng;  Martins, Rui Paulo
Adobe PDF | Favorite | TC[WOS]:8 TC[Scopus]:10  IF:4.0/3.7 | Submit date：2018/10/30
Analog-to-digital Conversion  Digital Background Calibration  Pipelined Adc  Split Adc  Opamp-sharing Technique