English | 繁體

Search in the results

UM

Browse/Search Results:  1-5 of 5 Help

Selected(0)Clear Items/Page:    Sort:
A 52.5-dB 2x Time-Interleaved 2.8-GS/s SAR ADC with 5-Bit/Cycle Time-Domain Quantization and a Compact Signal DAC Journal article
Zhao, Hongzhi, Zhang, Minglei, Zhu,Yan, Martins, R. P., Chan,Chi Hang. A 52.5-dB 2x Time-Interleaved 2.8-GS/s SAR ADC with 5-Bit/Cycle Time-Domain Quantization and a Compact Signal DAC[J]. IEEE Journal of Solid-State Circuits, 2023, 58(12), 3586-3597.
Authors:  Zhao, Hongzhi;  Zhang, Minglei;  Zhu,Yan;  Martins, R. P.;  Chan,Chi Hang
Favorite | TC[WOS]:1 TC[Scopus]:2  IF:4.6/5.6 | Submit date：2023/08/29
Analog-to-digital Converter (Adc)  Multi-bit/cycle Successive-approximation Register (Sar) Adc  Time-domain Quantization  Voltage-to-time (V2t) Buffer  Linearization  
Design of a Novel 2-bit Wideband Beam-Scanning Reconfigurable Intelligent Surface Conference paper
Hu, Qunqiang, Zeng, Xintu, Mao, Chunxu, Yang, Huiping, Wu, Qingqing, Tang, Jie, Lan Zhao, Xiao, Yin Zhang, Xiu. Design of a Novel 2-bit Wideband Beam-Scanning Reconfigurable Intelligent Surface[C], 2021.
Authors:  Hu, Qunqiang;  Zeng, Xintu;  Mao, Chunxu;  Yang, Huiping;  Wu, Qingqing; et al.
Favorite | TC[Scopus]:9 | Submit date：2023/03/30
2-bit  Beam-scanning  Pin Diodes  Ris  Wideband  
Defected ground structure of UWB chipless RFID tag for FMCW radar Conference paper
Meng-Ting Tu, Wai-Wa Choi, Pedro Cheong. Defected ground structure of UWB chipless RFID tag for FMCW radar[C], 2018.
Authors:  Meng-Ting Tu;  Wai-Wa Choi;  Pedro Cheong
Favorite | TC[WOS]:2 TC[Scopus]:5 | Submit date：2019/02/13
Chipless Rfid Tag  2-bit  U-slot Resonator  Microstrip  Defected Ground Structure  Chipless Rfid Tag  2-bit  U-slot Resonator  Microstrip  Defected Ground Structure  
A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration Journal article
Chan, Chi-Hang, Zhu, Yan, Zhang, Wai-Hong, Seng-Pan, U., Martins, Rui Paulo. A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2018, 53(3), 850-860.
Authors:  Chan, Chi-Hang;  Zhu, Yan;  Zhang, Wai-Hong;  Seng-Pan, U.;  Martins, Rui Paulo
Favorite | TC[WOS]:62 TC[Scopus]:68  IF:4.6/5.6 | Submit date：2018/10/30
1-then-2 B/cycle Sar Adc  Analog-to-digital Conversion  Background Offset Calibration  Multi-bit/cycle Sar Adc  Time Interleaving  
0.058 mm(2) 13 Gbit/s inductorless analogue equaliser with low-frequency equalisation compensating 15 dB channel loss Journal article
Balachandran, Arya, Chen, Yong, Choi, Pilsoon, Boon, Chirn Chye. 0.058 mm(2) 13 Gbit/s inductorless analogue equaliser with low-frequency equalisation compensating 15 dB channel loss[J]. ELECTRONICS LETTERS, 2018, 54(2).
Authors:  Balachandran, Arya;  Chen, Yong;  Choi, Pilsoon;  Boon, Chirn Chye
Favorite | TC[WOS]:7 TC[Scopus]:10  IF:0.7/0.9 | Submit date：2018/10/30
Equalisers  Circuit Feedback  Analogue Circuits  Random Sequences  Binary Sequences  Cmos Analogue Integrated Circuits  Inductorless Analogue Equaliser  Low-frequency Equalisation Compensation  Lfeq  Low-frequency Channel Loss  Active Feedback Topology  Negative Capacitance Circuit  Data Jitter  Pseudorandom Binary Sequence  Cmos Technology  Loss 15 Db  Bit Rate 13 gBit  s  Size 65 Nm  Voltage 1  2 v