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A 13-bit 60MS/s split pipelined ADC with background gain and mismatch error calibration Conference paper
Li Ding, Wenlan Wu, Sai-Weng Sin, Seng-Pan U, R.P.Martins. A 13-bit 60MS/s split pipelined ADC with background gain and mismatch error calibration[C]:IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA, 2013, 77-80.
Authors:  Li Ding;  Wenlan Wu;  Sai-Weng Sin;  Seng-Pan U;  R.P.Martins
Favorite | TC[WOS]:3 TC[Scopus]:3 | Submit date:2019/02/11