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A highly-linear successive-approximation front-end digitizer with built-in sample-and-hold function for pipeline/two-step ADC Conference paper
Weng-Ieng Mok, Pui-In Mak, U Seng-Pan, R.P. Martins. A highly-linear successive-approximation front-end digitizer with built-in sample-and-hold function for pipeline/two-step ADC[C], 2007, 1947-1950.
Authors:  Weng-Ieng Mok;  Pui-In Mak;  U Seng-Pan;  R.P. Martins
Favorite | TC[WOS]:1 TC[Scopus]:3 | Submit date：2019/02/11
On-Chip Unsteady Reference Voltage Compensation Techniques for Very-High-Speed Pipelined ADC Conference paper
Weng-Ieng Mok, Pui-In Mak, Seng-Pan U, R. P. Martins. On-Chip Unsteady Reference Voltage Compensation Techniques for Very-High-Speed Pipelined ADC[C], 2005, 276-280.
Authors:  Weng-Ieng Mok;  Pui-In Mak;  Seng-Pan U;  R. P. Martins
Favorite |  | Submit date：2019/02/28
High-speed  Pipelined Analog-to-digital Converter  Reference Voltage  Voltage Buffer  
Modeling of noise sources in reference voltage generator for very-high-speed pipelined ADC Conference paper
Weng-Ieng Mok, Pui-In Mak, Seng-Pan U, R.P. Martins. Modeling of noise sources in reference voltage generator for very-high-speed pipelined ADC[C], 2004, 5-8.
Authors:  Weng-Ieng Mok;  Pui-In Mak;  Seng-Pan U;  R.P. Martins
Favorite | TC[WOS]:2 TC[Scopus]:5 | Submit date：2019/02/11
I/Q imbalance modeling of quadrature wireless transceiver analog front-ends in SIMULINK Conference paper
Pui-In Mak, Weng-Ieng Mok, Seng-Pan U, R.P. Martins. I/Q imbalance modeling of quadrature wireless transceiver analog front-ends in SIMULINK[C], 2003, 2371-2374.
Authors:  Pui-In Mak;  Weng-Ieng Mok;  Seng-Pan U;  R.P. Martins
Favorite | TC[WOS]:0 TC[Scopus]:3 | Submit date：2019/02/11
Analog Front-end  Analog-double Quadrature Sampling  I/q Imbalance  Image-rejection  Quadrature Transceiver