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INSTITUTE OF MIC... [1]
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SIN SAI WENG [1]
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2019 [1]
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英語English [1]
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A 550μ W 20-kHz BW 100.8-dB SNDR Linear- Exponential Multi-Bit Incremental ΣΔ ADC with 256 Clock Cycles in 65-nm CMOS
Journal article
Wang, B., Sin,Sai Weng, Seng-Pan,S. P.U., Maloberti,Franco, Martins,Rui P.. A 550μ W 20-kHz BW 100.8-dB SNDR Linear- Exponential Multi-Bit Incremental ΣΔ ADC with 256 Clock Cycles in 65-nm CMOS[J]. IEEE Journal of Solid-State Circuits, 2019, 54(4), 1161-1172.
Authors:
Wang, B.
;
Sin,Sai Weng
;
Seng-Pan,S. P.U.
;
Maloberti,Franco
;
Martins,Rui P.
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TC[WOS]:
48
TC[Scopus]:
60
IF:
4.6
/
5.6
|
Submit date：2021/03/09
Analog-to-digital Converter (Adc)
Data Weighting Average
Dynamic Element Matching (Dem)
High Linearity
Incremental Adc (iAdc)
Linear-exponential Accumulation
Mismatch Error
Multi-bit
Notch
Sigma Delta
Two Phase
