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CLUT-CIM: A Capacitance Lookup Table-Based Analog Compute-in-Memory Macro With Signed-Channel Training and Weight Updating for Nonuniform Quantization Journal article
Fu, Yuzhao, Li, Jixuan, Yu, Wei Han, Un, Ka Fai, Chan, Chi Hang, Zhu, Yan, Martins, Rui P., Mak, Pui In. CLUT-CIM: A Capacitance Lookup Table-Based Analog Compute-in-Memory Macro With Signed-Channel Training and Weight Updating for Nonuniform Quantization[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2024.
Authors:  Fu, Yuzhao;  Li, Jixuan;  Yu, Wei Han;  Un, Ka Fai;  Chan, Chi Hang; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:5.2/4.5 | Submit date：2024/07/04
Capacitance Lookup Table (Clut)  Circuits  Common Information Model (Computing)  Compute-in-memory (Cim)  Energy Efficiency  High Energy Efficiency  In-memory Computing  Indexes  Nonuniform Quantization (Nuq)  Table Lookup  Thermometers  Weight Updating  
An FPGA-Based Energy-Efficient Reconfigurable Convolutional Neural Network Accelerator for Object Recognition Applications Journal article
Li, Jixuan, Un, Ka Fai, Yu, Wei Han, Mak, Pui In, Martins, Rui P.. An FPGA-Based Energy-Efficient Reconfigurable Convolutional Neural Network Accelerator for Object Recognition Applications[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2021, 68(9), 3143-3147.
Authors:  Li, Jixuan;  Un, Ka Fai;  Yu, Wei Han;  Mak, Pui In;  Martins, Rui P.
Favorite | TC[WOS]:40 TC[Scopus]:51  IF:4.0/3.7 | Submit date：2021/09/20
Computation Efficiency  Convolutional Neural Network (Cnn)  Fpga  Object Recognition  Reconfigurability  
A 50.4 GOPs/W FPGA-Based MobileNetV2 Accelerator using the Double-Layer MAC and DSP Efficiency Enhancement Conference paper
Li, Jixuan, Chen, Jiabao, Un, Ka Fai, Yu, Wei Han, Mak, Pui In, Martins, Rui P.. A 50.4 GOPs/W FPGA-Based MobileNetV2 Accelerator using the Double-Layer MAC and DSP Efficiency Enhancement[C], IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA:IEEE, 2021.
Authors:  Li, Jixuan;  Chen, Jiabao;  Un, Ka Fai;  Yu, Wei Han;  Mak, Pui In; et al.
Favorite | TC[WOS]:2 TC[Scopus]:5 | Submit date：2023/03/30
Computation Efficiency  Convolutional Neural Network (Cnn)  Fpga  Object Recognition  Reconfigurability