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60-dB SNDR 100-MS/s SAR ADCs With Threshold Reconfigurable Reference Error Calibration Journal article
Chan, Chi-Hang, Zhu, Yan, Li, Cheng, Zhang, Wai-Hong, Ho, Iok-Meng, Wei, Lai, Seng-Pan, U., Martins, Rui Paulo. 60-dB SNDR 100-MS/s SAR ADCs With Threshold Reconfigurable Reference Error Calibration[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2017, 52(10), 2576-2588.
Authors:  Chan, Chi-Hang;  Zhu, Yan;  Li, Cheng;  Zhang, Wai-Hong;  Ho, Iok-Meng; et al.
Favorite | TC[WOS]:38 TC[Scopus]:46  IF:4.6/5.6 | Submit date：2018/10/30
Reference Buffer  Reference Error Calibration  Successive Approximation Register (Sar) Analog-to-digital Converter (Adc)  Threshold Reconfigurable Comparator  
A 5mW 7b 2.4GS/s 1-then-2b/cycle SAR ADC with background offset calibration Conference paper
Chi-Hang Chan, Yan Zhu, Iok-Meng Ho, Wai-Hong Zhang, Seng-Pan U, Rui Paulo Martins. A 5mW 7b 2.4GS/s 1-then-2b/cycle SAR ADC with background offset calibration[C]. Institute of Electrical and Electronics Engineers Inc., 2017, 282-283.
Authors:  Chi-Hang Chan;  Yan Zhu;  Iok-Meng Ho;  Wai-Hong Zhang;  Seng-Pan U; et al.
Favorite | TC[WOS]:32 TC[Scopus]:37 | Submit date：2018/11/06
A 0.011mm2 60dB SNDR 100MS/s reference error calibrated SAR ADC with 3pF decoupling capacitance for reference voltages Conference paper
Chi-Hang Chan, Yan Zhu, Iok-Meng Ho, Wai-Hong Zhang, Chon-Lam Lio, Seng-Pan U, Rui Paulo Martins. A 0.011mm2 60dB SNDR 100MS/s reference error calibrated SAR ADC with 3pF decoupling capacitance for reference voltages[C], 2017, 145-148.
Authors:  Chi-Hang Chan;  Yan Zhu;  Iok-Meng Ho;  Wai-Hong Zhang;  Chon-Lam Lio; et al.
Favorite | TC[WOS]:6 TC[Scopus]:6 | Submit date：2019/02/11