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A 36-Gb/s 1.3-mW/Gb/s Duobinary-Signal Transmitter Exploiting Power-Efficient Cross-Quadrature Clocking Multiplexers with Maximized Timing Margin Journal article
Chen, Y., Mak, P. I., Boon, C.C., Martins, R. P.. A 36-Gb/s 1.3-mW/Gb/s Duobinary-Signal Transmitter Exploiting Power-Efficient Cross-Quadrature Clocking Multiplexers with Maximized Timing Margin[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2018, 3014-3026.
Authors:  Chen, Y.;  Mak, P. I.;  Boon, C.C.;  Martins, R. P.
Favorite |   IF:5.2/4.5 | Submit date：2022/01/25
Bandwidth (BW)  cross-quadrature clocking  data- dependent jitter (DDJ)  duobinary  multi-level signaling  CMOS  multiplexer (MUX)  figure-of-merit (FOM)  timing margin  latch  D-type flip-flop (DFF)  selector  
A 4.06 mW 10-bit 150 MS/s SAR ADC with 1.5-bit/cycle Operation for Medical Imaging Applications Journal article
Sunny S., Chen Y., Boon C.C.. A 4.06 mW 10-bit 150 MS/s SAR ADC with 1.5-bit/cycle Operation for Medical Imaging Applications[J]. IEEE Sensors Journal, 2018, 18(11), 4553-4560.
Authors:  Sunny S.;  Chen Y.;  Boon C.C.
Favorite | TC[WOS]:18 TC[Scopus]:21  IF:4.3/4.2 | Submit date：2019/02/14
1.5-bit/cycle  Adc  Capacitive Digital-to-analog Converter (Cdac)  Cmos  Error Correction  Low Power  Medical Imaging  Redundancy  Sar  Successive Approximation Register  
058 mm2 13 Gbit/s inductorless analogue equaliser with low-frequency equalisation compensating 15 dB channel loss Journal article
Balachandran A., Chen Y., Choi P., Boon C.C.. 058 mm2 13 Gbit/s inductorless analogue equaliser with low-frequency equalisation compensating 15 dB channel loss[J]. Electronics Letters, 2018, 54(2), 72-74.
Authors:  Balachandran A.;  Chen Y.;  Choi P.;  Boon C.C.
Favorite | TC[WOS]:6 TC[Scopus]:9 | Submit date：2019/02/14
A 0.013-mm2 0.53-mW/Gb/s 32-Gb/s Hybrid Analog Equalizer under 21-dB Channel Loss in 65-nm CMOS Journal article
Balachandran A., Chen Y., Boon C.C.. A 0.013-mm2 0.53-mW/Gb/s 32-Gb/s Hybrid Analog Equalizer under 21-dB Channel Loss in 65-nm CMOS[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017, 26(3), 599-603.
Authors:  Balachandran A.;  Chen Y.;  Boon C.C.
Favorite | TC[WOS]:16 TC[Scopus]:18 | Submit date：2019/02/14
Channel Loss  Cmos Equalizer  Continuoustime Linear Equalizer (Ctle)  Figure Of Merit (Fom)  Inductorless  Intersymbol Interference (Isi)  Low-frequency Equalization (Lfeq)