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A 362-TOPS/W Mixed-Signal MAC Macro With Sampling-Weight-Nonlinearity Cancellation and Dynamic-Amplified Accumulation Journal article
Zhang, Ran, Cen, Xueru, Un, Ka Fai, Guo, Mingqiang, Qi, Liang, Martins, Rui P., Sin, Sai Weng. A 362-TOPS/W Mixed-Signal MAC Macro With Sampling-Weight-Nonlinearity Cancellation and Dynamic-Amplified Accumulation[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2025.
Authors:  Zhang, Ran;  Cen, Xueru;  Un, Ka Fai;  Guo, Mingqiang;  Qi, Liang; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:5.2/4.5 | Submit date：2025/01/22
Dac Driver  Dynamic Amplifier  Machine Learning (Ml)  Mixed-signal Multiply-and-accumulate (Mac)  Multi-bit Neural Network  
Analyses Concerning the Phase Noise and Nonlinear Behavior of the Charge-Sharing Integrator-Based Hybrid PLL Journal article
Song, Jingrun, Yang, Xinyu, Liu, Jiaxu, Liu, Yueduo, Zhu, Zihao, Han, Zhengxuan, Zhang, Zehao, Liu, Jiaxin, Zhang, Hongshuai, Yin, Jun, Mak, Pui In, Yang, Shiheng. Analyses Concerning the Phase Noise and Nonlinear Behavior of the Charge-Sharing Integrator-Based Hybrid PLL[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2024.
Authors:  Song, Jingrun;  Yang, Xinyu;  Liu, Jiaxu;  Liu, Yueduo;  Zhu, Zihao; et al.
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Charge-sharing Integrator  Hybrid Pll (hPll)  Digital Pll (dPll)  Digitally Controlled Oscillator (Dco)  Jitter  Multi-rate  Nonlinearity  Phase Noise (Pn)  Prediction  Spur  Spectrum  
CLUT-CIM: A Capacitance Lookup Table-Based Analog Compute-in-Memory Macro With Signed-Channel Training and Weight Updating for Nonuniform Quantization Journal article
Fu, Yuzhao, Li, Jixuan, Yu, Wei Han, Un, Ka Fai, Chan, Chi Hang, Zhu, Yan, Martins, Rui P., Mak, Pui In. CLUT-CIM: A Capacitance Lookup Table-Based Analog Compute-in-Memory Macro With Signed-Channel Training and Weight Updating for Nonuniform Quantization[J]. IEEE Transactions on Circuits and Systems I-Regular Papers, 2024, 71(11), 4996-5004.
Authors:  Fu, Yuzhao;  Li, Jixuan;  Yu, Wei Han;  Un, Ka Fai;  Chan, Chi Hang; et al.
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:5.2/4.5 | Submit date：2024/07/04
Capacitance Lookup Table (Clut)  Circuits  Common Information Model (Computing)  Compute-in-memory (Cim)  Energy Efficiency  High Energy Efficiency  In-memory Computing  Indexes  Nonuniform Quantization (Nuq)  Table Lookup  Thermometers  Weight Updating  
A 97.8 GOPS/W FPGA-Based Residual-Block-Aware CNN Accelerator Featuring Multi-Clock PW2 Pipeline and Adaptive-Resolution Quantization Journal article
Li, Jixuan, Li, Ke, Un, Ka Fai, Yu, Wei Han, Martins, Rui P., Mak, Pui In. A 97.8 GOPS/W FPGA-Based Residual-Block-Aware CNN Accelerator Featuring Multi-Clock PW2 Pipeline and Adaptive-Resolution Quantization[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2024.
Authors:  Li, Jixuan;  Li, Ke;  Un, Ka Fai;  Yu, Wei Han;  Martins, Rui P.; et al.
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Convolutional Neural Network (Cnn)  Digital Signal Processing (Dsp)  Field-programmable Gate Array (Fpga)  Processing Unit (Pe) Utilization  Residual Block  
GSLP-CIM: A 28-nm Globally Systolic and Locally Parallel CNN/Transformer Accelerator With Scalable and Reconfigurable eDRAM Compute-in-Memory Macro for Flexible Dataflow Journal article
Zhan, Yi, Yu, Wei Han, Un, Ka Fai, Martins, Rui P., Mak, Pui In. GSLP-CIM: A 28-nm Globally Systolic and Locally Parallel CNN/Transformer Accelerator With Scalable and Reconfigurable eDRAM Compute-in-Memory Macro for Flexible Dataflow[J]. IEEE Transactions on Circuits and Systems I-Regular Papers, 2024.
Authors:  Zhan, Yi;  Yu, Wei Han;  Un, Ka Fai;  Martins, Rui P.;  Mak, Pui In
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:5.2/4.5 | Submit date：2024/12/05
Neural Network (Nn)  Transformer  Embedded Dynamic Random-access Memory (Edram)  Compute-in-memory (Cim)  Systolic  Flexible Dataflow  
0.4-V Supply, 12-nW Reverse Bandgap Voltage Reference With Single BJT and Indirect Curvature Compensation Journal article
Lee, Chon Fai, Chi-Wa, U., Martins, Rui P., Lam, Chi Seng. 0.4-V Supply, 12-nW Reverse Bandgap Voltage Reference With Single BJT and Indirect Curvature Compensation[J]. IEEE Transactions on Circuits and Systems I-Regular Papers, 2024, 71(11), 5040-5053.
Authors:  Lee, Chon Fai;  Chi-Wa, U.;  Martins, Rui P.;  Lam, Chi Seng
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:5.2/4.5 | Submit date：2024/12/05
Bandgap Voltage Reference  Reverse Bandgap  Nonlinear Current  Leakage Current  Temperature Coefficient  Internet Of Things  Energy Harvesting  
Analysis and Design of a 21.2-to-25.5-GHz Triple-Coil Transformer-Coupled QVCO Journal article
Zhao, Ya, Fan, Chao, Yin, Jun, Mak, Pui In, Geng, Li. Analysis and Design of a 21.2-to-25.5-GHz Triple-Coil Transformer-Coupled QVCO[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2024, 71(10), 4538-4549.
Authors:  Zhao, Ya;  Fan, Chao;  Yin, Jun;  Mak, Pui In;  Geng, Li
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:5.2/4.5 | Submit date：2024/11/05
Quadrature Voltage-controlled Oscillator (Qvco)  Phase Noise  Quadrature Phase Accuracy  Triple-coil  Transformer-coupled  Determinate Correlation  Bimodal Ambiguity  Tradeoff  Active Coupling Transistor  Alleviate  
An 840-to-970 MHz Multimodal Wake-Up Receiver With a Q-Equalized Antenna-ED Interface and 2-Dimensional Wake-Up Identification Journal article
Yang, Zhizhan, Zhang, Haochen, Yin, Jun, Martins, Rui P., Mak, Pui In. An 840-to-970 MHz Multimodal Wake-Up Receiver With a Q-Equalized Antenna-ED Interface and 2-Dimensional Wake-Up Identification[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2024.
Authors:  Yang, Zhizhan;  Zhang, Haochen;  Yin, Jun;  Martins, Rui P.;  Mak, Pui In
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:5.2/4.5 | Submit date：2024/10/10
Envelope Detector  Frequency-hopping  Internet Of Things (Iot)  Loop Antenna  Q-enhanced  Radio-frequency Identification (Rfid)  Ultra-low Power  Wake-up Receiver  
Two-Dimensional Cyclic Chaotic System for Noise-Reduced OFDM-DCSK Communication Journal article
Hua, Zhongyun, Wu, Zihua, Zhang, Yinxing, Bao, Han, Zhou, Yicong. Two-Dimensional Cyclic Chaotic System for Noise-Reduced OFDM-DCSK Communication[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2024, 72(1), 323-336.
Authors:  Hua, Zhongyun;  Wu, Zihua;  Zhang, Yinxing;  Bao, Han;  Zhou, Yicong
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Chaotic System  Chaos-based Practicality  Secure Communication  Chaotic Communication  
A Single-Inductor Multiple-Output DC–DC Converter With Fixed-Frequency Victim-Last Charge Control for Reduced Cross Regulation Journal article
Li, Yang, Huang, Mo, Martins, Rui P., Lu, Yan. A Single-Inductor Multiple-Output DC–DC Converter With Fixed-Frequency Victim-Last Charge Control for Reduced Cross Regulation[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2024, 71(8), 3904-3914.
Authors:  Li, Yang;  Huang, Mo;  Martins, Rui P.;  Lu, Yan
Favorite | TC[WOS]:0 TC[Scopus]:0  IF:5.2/4.5 | Submit date：2024/06/05
Simo Dc–dc Converter  Victim-last Control  Charge Control  Cross-regulation  Charge-error Calibration