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A 1024-Channel 268 nW/pixel 36x36 μm2/ch Data-Compressive Neural Recording IC for High-Bandwidth Brain-Computer Interfaces Conference paper
MoonHyung Jang, Wei-Han Yu, Changuk Lee, Maddy Hays, Pingyu Wang, Nick Vitale, Pulkit Tandon, Pumiao Yan, Pui-In Mak, Youngcheol Chae, E.J. Chichilnisky, Boris Murmann, Dante G. Muratore. A 1024-Channel 268 nW/pixel 36x36 μm2/ch Data-Compressive Neural Recording IC for High-Bandwidth Brain-Computer Interfaces[C], IEEE Xplore:IEEE, 2023.
Authors:  MoonHyung Jang;  Wei-Han Yu;  Changuk Lee;  Maddy Hays;  Pingyu Wang; et al.
Favorite | TC[Scopus]:5 | Submit date：2023/08/02
Brain  Compression  Interface  Neural  Recording  
An Auxiliary-Channel-Sharing Background Distortion and Gain Calibration Achieving >8dB SFDR Improvement over 4thNyquist Zone in 1GS/s ADC Conference paper
Wei, Lai, Zheng, Zihao, Markulic, Nereo, Lagos, Jorge, Martens, Ewout, Zhu, Yan, Chan, Chi Hang, Craninckx, Jan, Martins, Rui Paulo. An Auxiliary-Channel-Sharing Background Distortion and Gain Calibration Achieving >8dB SFDR Improvement over 4thNyquist Zone in 1GS/s ADC[C], 2021.
Authors:  Wei, Lai;  Zheng, Zihao;  Markulic, Nereo;  Lagos, Jorge;  Martens, Ewout; et al.
Favorite | TC[Scopus]:3 | Submit date：2021/09/20
Background Calibration  Nonlinearity  Pipelined Adc  Split-sar Adc  
A 20GS/s 8b Time-Interleaved Time-Domain ADC with Input-Independent Background Timing Skew Calibration Conference paper
Minglei Zhang, Yan Zhu, Chi-Hang Chan, Rui P. Martins. A 20GS/s 8b Time-Interleaved Time-Domain ADC with Input-Independent Background Timing Skew Calibration[C]:IEEE, 2021.
Authors:  Minglei Zhang;  Yan Zhu;  Chi-Hang Chan;  Rui P. Martins
Favorite | TC[Scopus]:10 | Submit date：2021/09/20
Background  Input Independent  Time Domain Adc  Time-interleaved Adc  Timing Skew Calibration  
A 10.4mW 50MHz-BW 80dB-DR Single-Opamp Third-Order CTSDM with SAB-ELD-Merged Integrator and 3-Stage Opamp Conference paper
Xing,Kai, Wang,Wei, Zhu,Yan, Chan,Chi Hang, Martins,Rui Paulo. A 10.4mW 50MHz-BW 80dB-DR Single-Opamp Third-Order CTSDM with SAB-ELD-Merged Integrator and 3-Stage Opamp[C], 2020.
Authors:  Xing,Kai;  Wang,Wei;  Zhu,Yan;  Chan,Chi Hang;  Martins,Rui Paulo
Favorite | TC[WOS]:7 TC[Scopus]:11 | Submit date：2020/12/04
3-stage Opamp  Ctsdm  Sab Integrator  
A 5MHz-BW, 86.1dB-SNDR 4X Time-Interleaved 2nd-Order ΔΣ Modulator with Digital Feedforward Extrapolation in 28nm CMOS Conference paper
Jiang,Dongyang, Qi,Liang, Sin,Sai Weng, Maloberti,Franco, Martins,R. P.. A 5MHz-BW, 86.1dB-SNDR 4X Time-Interleaved 2nd-Order ΔΣ Modulator with Digital Feedforward Extrapolation in 28nm CMOS[C], 2020.
Authors:  Jiang,Dongyang;  Qi,Liang;  Sin,Sai Weng;  Maloberti,Franco;  Martins,R. P.
Favorite | TC[WOS]:4 TC[Scopus]:11 | Submit date：2021/03/04
A 29mW 5GS/s Time-interleaved SAR ADC achieving 48.5dB SNDR with Fully-Digital Timing-Skew Calibration Based on Digital-Mixing Conference paper
Guo,Mingqiang, Mao,Jiaji, Sin,Sai Weng, Wei,Hegong, Martins,R. P.. A 29mW 5GS/s Time-interleaved SAR ADC achieving 48.5dB SNDR with Fully-Digital Timing-Skew Calibration Based on Digital-Mixing[C], IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA:IEEE, 2019, C76-C77.
Authors:  Guo,Mingqiang;  Mao,Jiaji;  Sin,Sai Weng;  Wei,Hegong;  Martins,R. P.
Adobe PDF | Favorite | TC[WOS]:24 TC[Scopus]:27 | Submit date：2021/03/09
A 550μW 20kHz BW 100.8DB SNDR Linear-Exponential Multi-Bit Incremental Converter with 256-cycles in 65NM CMOS Conference paper
Wang B., Sin S.-W., Seng-Pan U., Malobertr F., MartinMartinss R.P.. A 550μW 20kHz BW 100.8DB SNDR Linear-Exponential Multi-Bit Incremental Converter with 256-cycles in 65NM CMOS[C], 2019, 207-208.
Authors:  Wang B.;  Sin S.-W.;  Seng-Pan U.;  Malobertr F.;  MartinMartinss R.P.
Favorite | TC[WOS]:44 TC[Scopus]:12 | Submit date：2019/02/11
A 2PJ/Pixel/Direction MIMO Processing Based CMOS Image Sensor for Omnidirectional Local Binary Pattern Extraction and Edge Detection Conference paper
Zhong，Xiaopeng, Yu，Qian, Bermak，Amine, Tsui，Chi Ying, Law，May Kay. A 2PJ/Pixel/Direction MIMO Processing Based CMOS Image Sensor for Omnidirectional Local Binary Pattern Extraction and Edge Detection[C], 2018, 247-248.
Authors:  Zhong，Xiaopeng;  Yu，Qian;  Bermak，Amine;  Tsui，Chi Ying;  Law，May Kay
Favorite | TC[Scopus]:15 | Submit date：2021/03/11
A 77dB SNDR 12.5MHz Bandwidth 0-1 MASH ΣΔ ADC Based on the Pipelined-SAR Structure Conference paper
Song Y., Zhu Y., Chan C.-H., Geng L., Martins R.P.. A 77dB SNDR 12.5MHz Bandwidth 0-1 MASH ΣΔ ADC Based on the Pipelined-SAR Structure[C], 2018, 203-204.
Authors:  Song Y.;  Zhu Y.;  Chan C.-H.;  Geng L.;  Martins R.P.
Favorite | TC[WOS]:4 TC[Scopus]:21 | Submit date：2019/02/11
Σδ Adc  Pipelined-sar Adc  
A 550W 20kHz BW 100.8dB SNDR Linear-Exponential Multi-Bit Incremental Converter with 256-cycles in 65nm CMOS Conference paper
Wang, B., Sin, S. W., U, S.P., Maloberti, F., Martins, R. P.. A 550W 20kHz BW 100.8dB SNDR Linear-Exponential Multi-Bit Incremental Converter with 256-cycles in 65nm CMOS[C], US:IEEE, 2018.
Authors:  Wang, B.;  Sin, S. W.;  U, S.P.;  Maloberti, F.;  Martins, R. P.
Favorite |  | Submit date：2022/01/24
Incremental Converter  Analog to Digital Converter  ADC