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A 10.4-ENOB 120MS/s SAR ADC with DAC linearity calibration in 90nm CMOS Conference paper
Yan Zhu, Chi-Hang Chan, Seng-Pan U, R.P.Martins. A 10.4-ENOB 120MS/s SAR ADC with DAC linearity calibration in 90nm CMOS[C]:IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA, 2013, 69-72.
Authors:  Yan Zhu;  Chi-Hang Chan;  Seng-Pan U;  R.P.Martins
Favorite | TC[WOS]:15 TC[Scopus]:18 | Submit date:2019/02/11
A 13-bit 60MS/s split pipelined ADC with background gain and mismatch error calibration Conference paper
Li Ding, Wenlan Wu, Sai-Weng Sin, Seng-Pan U, R.P.Martins. A 13-bit 60MS/s split pipelined ADC with background gain and mismatch error calibration[C]:IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA, 2013, 77-80.
Authors:  Li Ding;  Wenlan Wu;  Sai-Weng Sin;  Seng-Pan U;  R.P.Martins
Favorite | TC[WOS]:3 TC[Scopus]:3 | Submit date:2019/02/11
A 0.127-mm2, 5.6-mW, 5th-order SC LPF with +23.5-dBm IIP3 and 1.5-to-15-MHz clock-defined bandwidth in 65-nm CMOS Conference paper
Yaohua Zhao, Pui-In Mak, Man-Kay Law, Rui P. Martins. A 0.127-mm2, 5.6-mW, 5th-order SC LPF with +23.5-dBm IIP3 and 1.5-to-15-MHz clock-defined bandwidth in 65-nm CMOS[C], 2013, 361-364.
Authors:  Yaohua Zhao;  Pui-In Mak;  Man-Kay Law;  Rui P. Martins
Favorite | TC[WOS]:7 TC[Scopus]:6 | Submit date:2019/02/11
Bandwidth  Cmos  Linearity  Lowpass Filter (Lpf)  Operational Transconductance Amplifier (Ota)  Software-defined Radio  Switched Capacitor (Sc)