Residential College | false |
Status | 即將出版Forthcoming |
Real-Time System Modeling and Verification Through Labeled Transition System Analyzer | |
Yang, Yilong1; Zu, Quan1,2; Ke, Wei3; Zhang, Miaomiao2; Li, Xiaoshan1 | |
2019 | |
Source Publication | IEEE Access
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Volume | 7Pages:26314-26323 |
Abstract | Model checking as a computer-assisted verification method is widely used in many fields to verify whether a design model satisfies the requirements specifications of the target system. In practice, it is difficult to design a system without the sophisticated requirements analysis. Unlike other model checking tools, the labeled transition system analyzer (LTSA) not only can specify the property specifications of the target system but also provides a structure diagram to specify the system architecture of the requirements model, which can be further used to design the target system. In this paper, we demonstrate the abilities of LTSA shipped with the classic case study of the steam boiler system. In the requirements analysis, the LTSA can specify the cyber and physical components of the target system and interactions between the components and the safety properties of the target system. In system design, the LTSA can automatically generate a start-up design model as the finite state process from the requirements model, and then a design model can be further accomplished by system architects and developers. Finally, the LTSA can automatically verify whether the design model meets the requirements specifications. Our work demonstrates the potential power of model checking tools can be applied and useful in software engineering for requirements analysis, system design, and verification. |
Keyword | Ltsa Model Checking Steam Boiler Uml |
DOI | 10.1109/ACCESS.2019.2899761 |
URL | View the original |
Language | 英語English |
WOS ID | WOS:000462088900001 |
Scopus ID | 2-s2.0-85062985493 |
Fulltext Access | |
Citation statistics | |
Document Type | Journal article |
Collection | University of Macau |
Affiliation | 1.Department of Computer and Information Science, Faculty of Science and Technology, University of Macau, C-Macau, 999087, China 2.School of Software Engineering, Tongji University, Shanghai, 201804, China 3.Macau Polytechnic Institute, C-Macau, 999087, China |
First Author Affilication | Faculty of Science and Technology |
Recommended Citation GB/T 7714 | Yang, Yilong,Zu, Quan,Ke, Wei,et al. Real-Time System Modeling and Verification Through Labeled Transition System Analyzer[J]. IEEE Access, 2019, 7, 26314-26323. |
APA | Yang, Yilong., Zu, Quan., Ke, Wei., Zhang, Miaomiao., & Li, Xiaoshan (2019). Real-Time System Modeling and Verification Through Labeled Transition System Analyzer. IEEE Access, 7, 26314-26323. |
MLA | Yang, Yilong,et al."Real-Time System Modeling and Verification Through Labeled Transition System Analyzer".IEEE Access 7(2019):26314-26323. |
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