UM
Patent NumberUS10644718B1
Status已授權 Granted
Single-loop linear-exponential multi-bit incremental analog-to-digital converter
2020-05-05
Application NumberUS16404791
Application Date2019-05-07
Rights HolderUniversity of Macau
Wang, Biao; Sin, Sai-Weng; Maloberti, Franco; Martins, Rui Paulo da Silva
Date Available2020-05-05
CountryUnited States
AbstractAn incremental analog-to-digital converter (IADC) with a two-phase linear-exponential accumulation loop for improving the signal to noise distortion ratio (SNDR) and the dynamic range (DR) is disclosed. The linear-exponential IADC includes an analog modulator and a decimation filter. The analog modulator has an input for receiving the analog input voltage and an output. The analog modulator includes an integrator, an adder, a quantizer, a noise-coupling path, a data weighted averaging (DWA) circuit, and a digital-to-analog converter (DAC). The decimation filter has an input for receiving signals from the output of the analog modulator. The decimation filter includes a 1st order accumulator, an exponential accumulator, and a decimator. The linear-exponential IADC is configured to operate with a linear phase for suppressing the thermal noise and an exponential phase for boosting the SQNR.
Language英語English
Open (Notice) NumberUS10644718B1
IPC Classification NumberH03M1/12 ; H03M1/08 ; H03M3/00 ; H04B1/00 ; H04L27/20
CPC Classification NumberH03M3/338 ; H03M3/34 ; H03M3/39 ; H03M3/462 ; H03M3/476 ; H04L27/0002 ; H03M1/08 ; H03M1/12 ; H03M3/454 ; H04B1/0021 ; H04L27/2032
Patent AgentThomas C. Meyers
AgencyBrown Rudnick LLP
Document TypePatent
CollectionUniversity of Macau
Recommended Citation
GB/T 7714
Wang, Biao,Sin, Sai-Weng,Maloberti, Franco,et al. Single-loop linear-exponential multi-bit incremental analog-to-digital converter. US10644718B1[P]. 2020-05-05.
APA Wang, Biao., Sin, Sai-Weng., Maloberti, Franco., & Martins, Rui Paulo da Silva (2019-05-07). Single-loop linear-exponential multi-bit incremental analog-to-digital converter.
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