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A Battery-Input Sub-1V Output 92.9% Peak Efficiency 0.3A/mm2Current Density Hybrid SC-Parallel-Inductor Buck Converter with Reduced Inductor Current in 65nm CMOS
Guigang Cai1; Yan Lu1; Rui Martins1,2
2022
Conference Name2022 IEEE International Solid-State Circuits Conference (ISSCC)
Volume2022-February
Pages312-314
Conference Date20-26 February 2022
Conference PlaceSan Francisco, CA, USA
Abstract

The profile of portable and wearable devices keeps shrinking, demanding high current density power management integrated circuits. Switched-capacitor (SC) converters and buck converters are two common solutions. Unregulated SC converters can achieve high power density and high efficiency for specific voltage conversion ratios (VCRs). However, to cover wide input and output voltage ranges, they require a reconfigurable topology with multiple VCRs, thus increasing the system complexity. On the other hand, buck converters can reach a good efficiency over a wide continuous VCR range. Yet, they need a bulky inductor, which significantly degrades the power density. To address the power density and efficiency tradeoff, hybrid converters composed of both inductor and capacitor are among popular solutions [1 - 4]. When compared with the traditional buck converter, these hybrid converters feature lower voltage swing (smaller current ripple) of the inductor, higher switching frequency, and a larger duty cycle (D) for the same VCR, alleviating the requirements on the inductor, and resulting in higher power density. Nevertheless, as all the output current IOUT goes through the inductor, this implies a large volume for small DCR and conduction loss P_COND_L. Recently, hybrid converters with reduced inductor current IL have emerged [5 - 7]. In these hybrid converters, the SC not only lowers down the voltage of the switch node, but also offers another current path to the output, reducing the inductor current. In this work, we propose an SC-parallel-inductor buck topology (which we refer to as CPL-Buck since in the proposd structure there is a capacitor that is always in parallel with the inductor) that can further reduce /L to less than 0.5IOUT, meaning a PCOND_L reduction of over 75% for the same DCR. Measurement results show that, for 1.2A maximum IOUT, 3-to-4.2V input to 0.6-to-1V output, the proposed CPL-Buck obtains a peak efficiency of 92.9% and a peak current density of 0.3A/mm2 with a power inductor as small as 1.6×0.8×0.8mm3.

DOI10.1109/ISSCC42614.2022.9731576
URLView the original
Language英語English
Scopus ID2-s2.0-85128287498
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Citation statistics
Document TypeConference paper
CollectionINSTITUTE OF MICROELECTRONICS
DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Corresponding AuthorYan Lu
Affiliation1.University of Macau, Macau, China
2.University of Lisboa, Lisbon, Portugal
First Author AffilicationUniversity of Macau
Corresponding Author AffilicationUniversity of Macau
Recommended Citation
GB/T 7714
Guigang Cai,Yan Lu,Rui Martins. A Battery-Input Sub-1V Output 92.9% Peak Efficiency 0.3A/mm2Current Density Hybrid SC-Parallel-Inductor Buck Converter with Reduced Inductor Current in 65nm CMOS[C], 2022, 312-314.
APA Guigang Cai., Yan Lu., & Rui Martins (2022). A Battery-Input Sub-1V Output 92.9% Peak Efficiency 0.3A/mm2Current Density Hybrid SC-Parallel-Inductor Buck Converter with Reduced Inductor Current in 65nm CMOS. , 2022-February, 312-314.
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