A 4 × 25Gb/s de-serializer using a baud-rate sampling clock and data recovery (BR-CDR) is presented for NIC optical interconnects. The integrating front-end (IFE) circuit is proposed to eliminate half of the sampling phases in the phase detector. The de-serializer employs a continuous-time linear equalizer, a phase-interpolation-based BR-CDR, and a source-series-terminated driver in each channel. The standing-wave distribution network delivers a low-jitter 12.5-GHz clock to all four channels across a 2-mm distance under low power consumption. Measurements show that the 4-channel de-serializer recovers 25-Gb/s inputs with significant inter-symbol interference, achieving a 1.2-Vppd output-swing with 3.43-ps RMS jitter, at the cost of 306-mW power.