| Status | 已發表Published |
| A 0.01mm2 1.2-pJ/bit 6.4-to-8Gb/s reference-less FD-less BBCDR using a deliberately-clock-selected strobe point based on a 2π/3-interval phase | |
Zhao, X. ; Chen, Y. ; Mak, P. I.; Martins, R. P.
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| 2021-06-06 | |
| Source Publication | WE02G
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| Abstract | This paper reports a single-loop full-rate bang-bang clock and data recovery (BBCDR) without both external reference and separate frequency detector. Specifically, our bang-bang phase detector incorporates the intrinsic three phases with a 2π/3 interval of the three-stage ring oscillator to deliberate the clock-selected strobe-point scheme, resulting in substantial hardware relaxation for automatic frequency acquisition. Together with the aid of a hybrid control circuit, the BBCDR can capture 6.4-to-8Gb/s data-rate variation automatically. Designed in a 65nm CMOS technology, our BBCDR achieves an energy efficiency of 1.2pJ/bit and 0.58UIPP jitter tolerance at 200MHz jitter frequency, while occupying a tiny area of ~0.01mm2. |
| Keyword | CDR CMOS Reference |
| Language | 英語English |
| The Source to Article | PB_Publication |
| PUB ID | 59434 |
| Document Type | Conference paper |
| Collection | University of Macau |
| Corresponding Author | Chen, Y. |
| Recommended Citation GB/T 7714 | Zhao, X.,Chen, Y.,Mak, P. I.,et al. A 0.01mm2 1.2-pJ/bit 6.4-to-8Gb/s reference-less FD-less BBCDR using a deliberately-clock-selected strobe point based on a 2π/3-interval phase[C], 2021. |
| APA | Zhao, X.., Chen, Y.., Mak, P. I.., & Martins, R. P. (2021). A 0.01mm2 1.2-pJ/bit 6.4-to-8Gb/s reference-less FD-less BBCDR using a deliberately-clock-selected strobe point based on a 2π/3-interval phase. WE02G. |
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