A modified KY converter is proposed in this work with single control method achieving high efficiency over wide loading range and small silicon area. An additional power switch is inserted in series with the inductor, allowing a better charging of the flying capacitor that is not limited by the DCM period of the proposed converter. The Double-Clock-Time (DCT) control can handle sleep to standby mode, achieving ultra-low quiescent current [1], but not for a full load of hundred mA. We combine DCT control with the power switch adaptive sizing technique to achieve high efficiency and wide output current range (100,000x). A clocked-feedback resistor network (CFRN) is also proposed to further reduce the quiescent current and silicon area. The proposed KY converter is fabricated in a 65nm CMOS, with 0.158 mm2, achieving 95% peak efficiency.