This paper presents a 2.3 GS/s 12-way timeinterleaved pipelined-SAR ADC achieving 1.1 GHz input bandwidth with 47.4 dB SNDR. Here, we propose a hierarchical interleaving with passively shared sub-sampling front-end to eliminate the timing skews, thus avoiding the timing calibration for design simplicity as well as better area and power efficiency. To provide a fast signal transfer with good power efficiency to the sub-ADCs, the power and bandwidth trades-off by using passive sharing or active buffers are analyzed according to our developed mathematic model. The analysis is based on two scenarios: noise and matching limited sampling. Moreover, we propose a boosting-capacitorsharing (BCS) technique to enhance the compactness of the time-interleaved sampling front-end, which is particularly critical in the design when omitting the time calibration. Measurement results on a 65 nm CMOS prototype operated at 2.3 GS/s and 1.2 V supply show 31 mW total power consumption with a SNDR of 47.4 dB @Nyquist leading to a FOM of 69 fJ/conv.step.