This paper presents a two-path discrete-time (DT) third-order sigma-delta (ΣΔ) modulator with an extra zero in the noise transfer function (NTF) located at z=-1, reducing the NTF coefficients of intermediate terms for optimal design. Applying polyphase decomposition of the NTF, the proposed ΣΔ modulator is implemented by a two-path architecture with cross-coupling branches. The 65-nm CMOS experimental chip running at a sampling rate of 340 MHz achieves a DR of 68.8 dB and a SNDR of 65.4 dB for a 10-MHz signal bandwidth, occupying an active area of 0.2257 mm2 and consuming 19.47 mW from a 1.2-V supply.