Wearable and sensing electronics are evolving towards energy harvesting from the environment (e.g. thermal and solar energy). Ultra-low-voltage (ULV) circuits that allow direct-powering by sub-0.5 V energy sources can maximize the power efficiency. This work is a 0.4 V 65 nm CMOS relaxation oscillator with bootstrapped logic gates and outputs. The bootstrapped logic gates enable an output swing of 1.15 V surmounting the adverse effect of ULV digital circuits without extra voltage source. The ULV comparator with bulk-driven-inputs shows an 18 dB gain with 3 cascaded stages. Also, featuring a background delay-time cancellation scheme, the 3.3 MHz relaxation oscillator with built-in calibration exhibits a frequency deviation of ±0.71% and ±0.57% against temperature (−30 to 100 °C) and voltage (0.36 to 0.44 V) variations, respectively, from Monte-Carlo simulations (N=30). The simulated power consumption is 6.4 μW, resulting in an energy efficiency of 1.9 pJ per cycle.