A 5-bit 1.25-GS/s 4x-Capacitive-Folding Flash ADC in 65nm CMOS

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	A 5-bit 1.25-GS/s 4x-Capacitive-Folding Flash ADC in 65nm CMOS
	Chan, C.H.; Zhu, Y.; Sin, S. W.; U, S.P.; Martins, R. P.; Maloberti, F.
	2013-09-01
Source Publication	IEEE Journal of Solid-State Circuits
ISSN	0018-9200
Pages	2154-2169
Abstract	This paper presents a 5-bit 1.25-GS/s folding flash ADC. The prototype achieves a folding factor of four with a capacitive folding technique that only consumes dynamic power. Incorporated with various calibration schemes, folding errors and the comparator’s threshold inaccuracies are corrected, thus allowing a low input capacitance of 80 fF. The design is fabricated using 65-nm digital CMOS technology and occupies 0.007 mm . The maximum DNL and INL post calibration are 0.67 and 0.47 LSB, respectively. Measurement results show that the ADC can achieve 1.25 GS/s at 1-V supply with a total power consumption of 595uW. In addition, it exhibits a mean ENOB of 4.8b at dc among ten chips, which yields an FoM of 17 fJ/conversion-step.
Keyword	Analog-to-Digital Converters ADC
URL	View the original
Language	英語English
The Source to Article	PB_Publication
PUB ID	10523
Document Type	Journal article
Collection	DEPARTMENT OF PSYCHOLOGY
Recommended Citation GB/T 7714	Chan, C.H.,Zhu, Y.,Sin, S. W.,et al. A 5-bit 1.25-GS/s 4x-Capacitive-Folding Flash ADC in 65nm CMOS[J]. IEEE Journal of Solid-State Circuits, 2013, 2154-2169.
APA	Chan, C.H.., Zhu, Y.., Sin, S. W.., U, S.P.., Martins, R. P.., & Maloberti, F. (2013). A 5-bit 1.25-GS/s 4x-Capacitive-Folding Flash ADC in 65nm CMOS. IEEE Journal of Solid-State Circuits, 2154-2169.
MLA	Chan, C.H.,et al."A 5-bit 1.25-GS/s 4x-Capacitive-Folding Flash ADC in 65nm CMOS".IEEE Journal of Solid-State Circuits (2013):2154-2169.

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