Status已發表Published
A 22.4μW 80dB SNDR ΣΔ Modulator with Passive Analog adder and SAR Quantizer for EMG Application
Chen, Z; Jiang, Y; Cai, C.Y.; Wei, H.G.; Sin, S. W.; U, S.P.; Wang, Z.; Martins, R. P.
2012-12-12
Source PublicationIEEE Asian Solid-State Circuit Conference – A-SSCC
Pages257-260
Publication PlaceUS
PublisherIEEE
AbstractA Feed-Forward (FF) multi-bit ΣΔ modulator with passive analog adder and 4-bit Successive Approximation (SA) quantizer is presented. The modulator covers the 10KHz bandwidth according to electromyography application. The design utilizes the same DAC array of the SAR quantizer to realize analog summation for the FF signal, which significantly reduces the power dissipation and the silicon area. The modulator operates at 1MS/s with IV supply. The prototype chip implemented in 65nm CMOS achieves 80dB SNDR and 81dB DR with 22.4μW power consumption. The Figure of Merit (FoM) is 0.13 pJ/conv.-step.
KeywordAnalog-to-Digital Converters ADC
URLView the original
Language英語English
The Source to ArticlePB_Publication
PUB ID10653
Document TypeConference paper
CollectionDEPARTMENT OF PUBLIC HEALTH AND MEDICINAL ADMINISTRATION
Corresponding AuthorChen, Z
Recommended Citation
GB/T 7714
Chen, Z,Jiang, Y,Cai, C.Y.,et al. A 22.4μW 80dB SNDR ΣΔ Modulator with Passive Analog adder and SAR Quantizer for EMG Application[C], US:IEEE, 2012, 257-260.
APA Chen, Z., Jiang, Y., Cai, C.Y.., Wei, H.G.., Sin, S. W.., U, S.P.., Wang, Z.., & Martins, R. P. (2012). A 22.4μW 80dB SNDR ΣΔ Modulator with Passive Analog adder and SAR Quantizer for EMG Application. IEEE Asian Solid-State Circuit Conference – A-SSCC, 257-260.
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