This paper presents a Time-Interleaved pipelined-SAR ADC with on-chip offset cancellation technique. The design reuses the SAR ADC to perform offset cancellation, thus saving calibration costs. The inter-stage gain of 8 is implemented in a 6-bit capacitive DAC with a flip around operation. A capacitive attenuation used in both the 1st-and 2nd-DACs significantly reduces the power dissipation and optimizes conversion speed. The detailed circuit implementation of the sub-threshold op-amp is discussed, and the possible limits caused by non-idealities are analyzed for a proper correction in the design. These include the inter-stage-gain error and various channel mismatches of offset, gain, and timing. Measurements of a 65nm CMOS prototype operating at 160MS/s and 1.1V supply show an SNDR of 55.4dB and 2.72mW total power consumption