Wireless communication systems and Ethernet networks call for moderate-resolution GS/s energy-efficient ADCs. While previous work [1] shows that the multi-bit per cycle SAR ADC can achieve low power due to various hardware reduction techniques, there are still a few limitations that restrain this architecture. First, the pre-charge slows down the logic and the DAC settling, especially during the MSB conversions. Second, unlike the offset among sub-channels of interleaving SAR ADCs, which can be easily calibrated in the background at the ADC backend [2], the offsets of the comparators in multi-bit SAR ADCs lead to a large sub-ranging error. Such offset is often calibrated in the foreground [1][3] but cannot track voltage and temperature (V&T) variations. This paper presents a 1-then-2b/cycle SAR architecture which removes conventional pre-charging and simultaneously minimizes the logic circuitry complexity to that of a 1b/cycle SAR. The comparator offsets are calibrated in the background without any extra phases or input references. With 2× time interleaving, the prototype achieves 2.4GS/s using a 0.9V supply in 28nm CMOS, leading to a 25.3fJ/conv-step Walden FoM at Nyquist input.