This brief presents a 2nd-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with a lossless integrator for achieving low power and high NS efficiency. It implements the lossless integrator through a ping-pong structure and a low-gain dynamic amplifier with moderate gain variation tolerance. Taking advantage of the lossless integrator, a low resolution SAR ADC is allowed under the same quantization noise budget. Fabricated in a 65-nm CMOS process, the prototype 8-bit NS-SAR ADC consumes 1.24 mW at 1.2 V while operating at 100 MS/s. It achieves a peak signal to noise and distortion ratio (SNDR) of 77 dB over a bandwidth of 3.125 MHz at the oversampling ratio (OSR) of 16, leading to an SNDR-based Schreier figure of merit (FoM) of 171 dB.