A 1.7-to-2.7GHz 35-38% PAE Multiband CMOS Power Amplifier Employing a Digitally-Assisted Analog Pre-distorter (DAAPD) Reconfigurable Linearization Technique

doi:10.1109/TCSII.2021.3080831

UM > THE STATE KEY LABORATORY OF ANALOG AND MIXED-SIGNAL VLSI (UNIVERSITY OF MACAU)

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	A 1.7-to-2.7GHz 35-38% PAE Multiband CMOS Power Amplifier Employing a Digitally-Assisted Analog Pre-distorter (DAAPD) Reconfigurable Linearization Technique
	Mariappan, Selvakumar 1; Rajendran, Jagadheswaran 2; Chen, Yong3 ; Mak, Pui In3 ; Martins, Rui P.4
	2021-05-17
Source Publication	IEEE Transactions on Circuits and Systems II: Express Briefs
ISSN	1549-7747
Volume	68 Issue:11 Pages:3381-3385
Abstract	This brief presents a CMOS power amplifier (PA) employing a digitally-assisted analog pre-distorter (DAAPD) reconfigurable linearization technique to reduce the back-off output power (PBO) for multiband operation. The proposed DAAPD optimizes the interstage load impedance between the driver and the main stage by changing the transconductance of the driver amplifier and its active load.We also utilize the DAAPD to optimize the PA when subjected to process-voltagetemperature (PVT) variations. Fabricated in 130-nm CMOS, the DAAPDPA operates from 1.7 to 2.7 GHz with a 3 dB back-off output power efficiency of 35% to 38% while fulfilling the stringent adjacent channel leakage ratio (ACLR) and error vector magnitude (EVM) requirements of a 20-MHz 16-QAM LTE signal. With a continuous wave (CW) signal, the DAAPD-PA achieves a maximum output power of 27 to 28 dBm across frequencies of interest with supply headroom of 3.3 V. Finally, the DAAPD-PA covers 20 LTE bands with reduced back-off output power.
Keyword	Power Amplifier (Pa) Cmos Digitally-assisted Analog Predistorter (Daapd) Back-off Output Power (Pbo) Adjacent Channel Leakage Ratio (Aclr) And Error Vector Magnitude (Evm) Power-added Efficiency (Pae) Long-term Evolution (Lte)
DOI	10.1109/TCSII.2021.3080831
URL	View the original
Indexed By	SCIE
Language	英語English
WOS Research Area	Engineering
WOS Subject	Engineering, Electrical & Electronic
WOS ID	WOS:000711728300004
Publisher	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC445 HOES LANE, PISCATAWAY, NJ 08855-4141
Scopus ID	2-s2.0-85107204165
Fulltext Access	View Full-Text via DOI View Full-Text via Web of Science View Full-Text via Scopus
Citation statistics
Document Type	Journal article
Collection	THE STATE KEY LABORATORY OF ANALOG AND MIXED-SIGNAL VLSI (UNIVERSITY OF MACAU) Faculty of Science and Technology INSTITUTE OF MICROELECTRONICS DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Corresponding Author	Rajendran, Jagadheswaran
Affiliation	1.Collaborative Microelectronic Design Excellence Centre (CEDEC), Engineering Campus, Universiti Sains Malaysia, Penang, Malaysia. 2.Collaborative Microelectronic Design Excellence Centre (CEDEC), Engineering Campus, Universiti Sains Malaysia, Penang, Malaysia. (e-mail: [email protected]) 3.State-Key Laboratory of Analog and Mixed-Signal VLSI and IME/ECE-FST, University of Macau, Macao, China. 4.State-Key Laboratory of Analog and Mixed-Signal VLSI and IME/ECE-FST, University of Macau, Macao, China, also with leave from Instituto Superior Técnico, Universidade de Lisboa, Portugal.
Recommended Citation GB/T 7714	Mariappan, Selvakumar,Rajendran, Jagadheswaran,Chen, Yong,et al. A 1.7-to-2.7GHz 35-38% PAE Multiband CMOS Power Amplifier Employing a Digitally-Assisted Analog Pre-distorter (DAAPD) Reconfigurable Linearization Technique[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2021, 68(11), 3381-3385.
APA	Mariappan, Selvakumar., Rajendran, Jagadheswaran., Chen, Yong., Mak, Pui In., & Martins, Rui P. (2021). A 1.7-to-2.7GHz 35-38% PAE Multiband CMOS Power Amplifier Employing a Digitally-Assisted Analog Pre-distorter (DAAPD) Reconfigurable Linearization Technique. IEEE Transactions on Circuits and Systems II: Express Briefs, 68(11), 3381-3385.
MLA	Mariappan, Selvakumar,et al."A 1.7-to-2.7GHz 35-38% PAE Multiband CMOS Power Amplifier Employing a Digitally-Assisted Analog Pre-distorter (DAAPD) Reconfigurable Linearization Technique".IEEE Transactions on Circuits and Systems II: Express Briefs 68.11(2021):3381-3385.

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