To suppress the gain error from dynamic-power amplifiers, recently presented approaches including gain-error shaping (GES) [1], digital amplifiers [2] and closed-loop dynamic amplifiers [3] are promising alternatives for calibrations. However, due to the high gain and stability requirements, it is difficult to run the closed-loop dynamic amplifier [3] at high speed. The digital amplifier [2] calls for a low-noise comparator, which is both power-inefficient and high-speed unfriendly. The GES shapes the inter-stage gain (ISG) error of the SAR-assisted pipeline ADC into high frequencies [1]. Nevertheless, its extra 1st stage DAC and digital error feedback significantly confines the overall pipelined speed. Rather than a dedicated effort to handle the ISG error, this paper explores an architectural approach that inherently tolerates it. We incorporate together the shaping of the gain and quantization errors, thereby omitting any additional feedback operations or hardware. Further, with the partial-interleaving (PI) 1st stage, the noise-shaping (NS) SAR-assisted pipeline ADC (N-0 MASH) runs at 400MHz with 25MHz bandwidth (BW). It demonstrates a gain-error tolerability in the 3dB-SNDR-deviation of -16% to + 12#x0025; from a nominal 75dB SNDR.