Per-core dynamic voltage frequency scaling (DVFS) can significantly improve the overall energy efficiency of multi-core processors by enabling each core to operate independently across a wide voltage-frequency range, where each core can be supplied by fully-integrated low dropout regulators (LDOs) that have sub-ns transient response, large load capability (>1A), high accuracy and wide input/output voltage range. A conventional analog LDO needs to solve the stability problem caused by the large power transistor for high current. Most of the prior fully-integrated analog LDOs are only capable of delivering a load current of <250 mA, which is insufficient to supply a high-performance processor. Digital LDOs [1]-[2] usually require high speed multi-bit ADC and compensation logic, complicating the design. Switching LDOs [3]-[5] which employ a fast on-off signal to drive the power transistor may meet the above requirements, but have relatively large output ripples, especially in the fast corner and large VDS conditions.