This work presents a multi-loop digital low dropout regulator (DLDO), with analog-proportional (AP) and digital-integral (DI) controls. The DI part is implemented with shift-register-based coarse-fine tuning for good output DC accuracy and fast recovery. Meanwhile, the AP part, based on an improved low-supply flipped-voltage-follower (FVF), can response fast to the load step and supply ripple. A replica loop is used to adaptively control the AP current for a sufficient dynamic current to against supply ripple, and thus further enhances the power supply rejection (PSR). When the load current is smaller than the digital least significant bit (LSB) current, the AP part takes over the LDO control. In such case, the limit cycle oscillation (LCO) is eliminated, and no longer limits the minimum load current to be zero. Implemented in a 65nm CMOS process, a 0.38ps Figure of merit (FoM) and 22dB PSR at 1MHz are measured at 0.6V supply.