| Residential College | false |
| Status | 已發表Published |
| A 29mW 5GS/s Time-interleaved SAR ADC achieving 48.5dB SNDR with Fully-Digital Timing-Skew Calibration Based on Digital-Mixing | |
Guo,Mingqiang1,2 ; Mao,Jiaji1,2; Sin,Sai Weng1,2 ; Wei,Hegong3; Martins,R. P.1,2,4
| |
| 2019-06-01 | |
| Conference Name | 33rd Symposium on VLSI Circuits, VLSI Circuits 2019 |
| Source Publication | IEEE Symposium on VLSI Circuits, Digest of Technical Papers
 |
| Volume | 2019-June |
| Pages | C76-C77 |
| Conference Date | JUN 09-14, 2019 |
| Conference Place | Kyoto, JAPAN |
| Country | Japan |
| Publication Place | IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA |
| Publisher | IEEE |
| Abstract | This paper presents a 5GS/s 16-way Time-Interleaved SAR ADC in 28nm CMOS, proposing a fully-digital background timing-skew calibration based on digital mixing, without adding any extra analog circuits. We implement the sub-channel SAR with a splitting-combined monotonic switching procedure. The prototype ADC achieves 48.5dB SNDR at Nyquist rate, while the power consumption is 29mW leading to a Walden FOM of 26.7fJ/conv-step. |
| DOI | 10.23919/VLSIC.2019.8778077 |
| URL | View the original |
| Indexed By | CPCI-S ; EI |
| Language | 英語English |
| WOS Research Area | Engineering |
| WOS Subject | Engineering, Electrical & Electronic |
| WOS ID | WOS:000531736500026 |
| Scopus ID | 2-s2.0-85073906848 |
| Fulltext Access | |
| Citation statistics | |
| Document Type | Conference paper |
| Collection | THE STATE KEY LABORATORY OF ANALOG AND MIXED-SIGNAL VLSI (UNIVERSITY OF MACAU) Faculty of Science and Technology INSTITUTE OF MICROELECTRONICS DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING |
| Corresponding Author | Sin,Sai Weng |
| Affiliation | 1.State-Key Laboratory of Analog and Mixed-Signal VLSI/Institute of Microelectronics-IME, University of Macau, Macao, China 2.DECE/FST, University of Macau, Macao, China 3.University of Texas at Austin, Austin, United States 4.Instituto Superior Tecnico ,Universidade de Lisboa, Portugal |
| First Author Affilication | University of Macau; Faculty of Science and Technology |
| Corresponding Author Affilication | University of Macau; Faculty of Science and Technology |
| Recommended Citation GB/T 7714 | Guo,Mingqiang,Mao,Jiaji,Sin,Sai Weng,et al. A 29mW 5GS/s Time-interleaved SAR ADC achieving 48.5dB SNDR with Fully-Digital Timing-Skew Calibration Based on Digital-Mixing[C], IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA:IEEE, 2019, C76-C77. |
| APA | Guo,Mingqiang., Mao,Jiaji., Sin,Sai Weng., Wei,Hegong., & Martins,R. P. (2019). A 29mW 5GS/s Time-interleaved SAR ADC achieving 48.5dB SNDR with Fully-Digital Timing-Skew Calibration Based on Digital-Mixing. IEEE Symposium on VLSI Circuits, Digest of Technical Papers, 2019-June, C76-C77. |
| Files in This Item: | Download All | |||||
| File Name/Size | Publications | Version | Access | License | ||
| A_29mW_5GS_s_Time-in（228KB） | 会议论文 | 开放获取 | CC BY-NC-SA | View Download | ||
Items in the repository are protected by copyright, with all rights reserved, unless otherwise indicated.
Edit Comment