| Residential College | false |
| Status | 已發表Published |
| A 10.4mW 50MHz-BW 80dB-DR Single-Opamp Third-Order CTSDM with SAB-ELD-Merged Integrator and 3-Stage Opamp | |
Xing,Kai1; Wang,Wei1; Zhu,Yan1 ; Chan,Chi Hang1 ; Martins,Rui Paulo1,2
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| 2020-06 | |
| Conference Name | 2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020 |
| Source Publication | IEEE Symposium on VLSI Circuits, Digest of Technical Papers
 |
| Volume | 2020-June |
| Conference Date | 2020/06/16-2020/06/19 |
| Conference Place | Honolulu, HI, USA |
| Abstract | This paper presents a wideband and energy-efficient single-loop 3 order CTSDM enabled by an ELD-SAB-Merged integrator and a 3-stage opamp. We utilize only a single DAC and opamp to accomplish the ELD compensation in the SAB structure. While featuring a PSQ technique and a 1 order NS-SAR, the 28nm prototype achieves a 74.4dB SNDR in a 50MHz BW and consumes 10.4mW with 171.2dB FoM. |
| Keyword | 3-stage Opamp Ctsdm Sab Integrator |
| DOI | 10.1109/VLSICircuits18222.2020.9162797 |
| URL | View the original |
| Indexed By | CPCI-S |
| Language | 英語English |
| WOS Research Area | Computer Science ; Engineering |
| WOS Subject | Computer Science, Hardware & Architecture ; Engineering, Electrical & Electronic |
| WOS ID | WOS:000621657500024 |
| Scopus ID | 2-s2.0-85090213797 |
| Fulltext Access | |
| Citation statistics | |
| Document Type | Conference paper |
| Collection | Faculty of Science and Technology THE STATE KEY LABORATORY OF ANALOG AND MIXED-SIGNAL VLSI (UNIVERSITY OF MACAU) INSTITUTE OF MICROELECTRONICS DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING |
| Corresponding Author | Chan,Chi Hang |
| Affiliation | 1.State-Key Laboratory of Analog and Mixed Signal VLSI,Ime and DECE/FST,University of Macau,Macao 2.Instituto Superior Técnico,Universidade de Lisboa,Portugal |
| First Author Affilication | Faculty of Science and Technology |
| Corresponding Author Affilication | Faculty of Science and Technology |
| Recommended Citation GB/T 7714 | Xing,Kai,Wang,Wei,Zhu,Yan,et al. A 10.4mW 50MHz-BW 80dB-DR Single-Opamp Third-Order CTSDM with SAB-ELD-Merged Integrator and 3-Stage Opamp[C], 2020. |
| APA | Xing,Kai., Wang,Wei., Zhu,Yan., Chan,Chi Hang., & Martins,Rui Paulo (2020). A 10.4mW 50MHz-BW 80dB-DR Single-Opamp Third-Order CTSDM with SAB-ELD-Merged Integrator and 3-Stage Opamp. IEEE Symposium on VLSI Circuits, Digest of Technical Papers, 2020-June. |
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