The fundamental limitation of Nyquist analog-to-digital converter (ADC) architectures toward high speed is meta-stability. It refers to the inability of a latched comparator to produce a valid decision in a certain available time. This issue is usually severe in high-speed successive approximation register (SAR) ADCs due to their serial conversion scheme, which includes the regeneration and the reset process of the comparator in a feedback loop, thus significantly reducing the available time for the regeneration. Our analysis considers the probability of metastability errors as a function of their magnitude and is customized for a timer-based asynchronous SAR ADC (with loop time-out). The resulting framework can also quantify the metastability in a synchronous architecture, and we provide a numerical comparison. To validate the analysis, measurement results of an 8-bit 130-MS/s SAR ADC in 90-nm CMOS are provided.