This paper details the theory and implementation of an inverse-class-F (class-F−1) CMOS oscillator. It features: 1) a single-ended PMOS-NMOS-complementary architecture to generate the differential outputs and 2) a transformer-based two-port resonator to boost the drain-to-gate voltage gain (AV) while creating two intrinsic-high-Q impedance peaks at the fundamental ( fLO) and double (2 fLO) oscillation frequencies. The enlarged second harmonic voltage extends the flat span in which the impulse sensitivity function (ISF) is minimum, and the amplified gate voltage swing reduces the current commutation time, thereby lowering the –gm transistor’s noise-to-phase noise (PN) conversion. Prototyped in 65-nm CMOS, the class-F−1 oscillator at 4 GHz exhibits a PN of –144.8 dBc/Hz at a 10-MHz offset, while offering a tuning range of 3.5–4.5 GHz. The corresponding figure of merit (FoM) is 196.1 dBc/Hz, and the die area is 0.14 mm2