This paper proposes a 4-fold multistage Switched-Capacitor (SC) interpolation filter with 5 MHz passband and 54 MHz output sampling rate for NTSC/PAL digital video signal processing systems. The circuit implements an impulse sampled halfband interpolation with 23- and 7-tap FIR filtering in 1stand 2nd-stage respectively for achieving a linear-phase response. A novel area-efficient technique including symmetrical-coefficient-sharing and spread-reduction is proposed in this transversal SC circuit embedding minimized mismatch-free analog delay lines with accurate, wideband gain- and offset-compensation. This filter is designed with optimized speed of the analog components in 0.35 /spl mu/m CMOS technology and expected to consume about 2 mm/sup 2/ active area and 90 mW at 3.0 V supply